Gate driving circuit and driving method thereof, and display device

Patent metadata

Field	Value
Publication number	US-2025166541-A1
Application number	US-202418928569-A
Country	US
Kind code	A1
Filing date	Oct 28, 2024
Priority date	Nov 20, 2023
Publication date	May 22, 2025
Grant date	—

Abstract

A gate driving circuit and a driving method thereof, and a display device that belong to the field of display technology. The gate driving circuit includes an input module and a storage module. The input module is connected to each of a first node and a signal input terminal of the gate driving circuit and configured to control the potential of the first node according to the potential of the signal input terminal. An input terminal of the storage module is connected to the first node. The storage module is configured to store the potential of the first node and control the potential of an output terminal of the storage module according to the potential of the first node.

First claim

What is claimed is:

1 . Agate driving circuit, comprising:
an input module, wherein the input module is connected to each of a first node and a signal input terminal of the gate driving circuit and configured to control a potential of the first node according to a potential of the signal input terminal; and a storage module, wherein an input terminal of the storage module is connected to the first node, and the storage module is configured to store the potential of the first node and control a potential of an output terminal of the storage module according to the potential of the first node.

2 . The gate driving circuit according to claim 1 , further comprising an output module, wherein the output module is connected between the output terminal of the storage module and a signal output terminal of the gate driving circuit, and the output module is configured to control a potential of the signal output terminal of the gate driving circuit according to the potential of the output terminal of the storage module, wherein
the input module is configured to transmit a potential hop of the signal input terminal to the first node in a delayed manner; the storage module is configured to invert the potential of the first node and then outputs the inverted potential of the first node to the output terminal of the storage module; and the output module is configured to invert the potential of the output terminal of the storage module and then outputs the inverted potential of the output terminal of the storage module to the signal output terminal of the gate driving circuit.

3 . The gate driving circuit according to claim 1 , wherein the storage module comprises:
a first inversion unit, wherein a control terminal of the first inversion unit is connected to the first node, a first input terminal of the first inversion unit is connected to a first power terminal, a second input terminal of the first inversion unit is connected to a second power terminal, and an output terminal of the first inversion unit is connected to the output terminal of the storage module; and a second inversion unit, wherein a control terminal of the second inversion unit is connected to the output terminal of the storage module, a first input terminal of the second inversion unit is connected to the first power terminal, a second input terminal of the second inversion unit is connected to the second power terminal, and an output terminal of the second inversion unit is connected to the first node; wherein the first inversion unit comprises a first transistor and a second transistor, a gate of the first transistor and a gate of the second transistor are each connected to the first node, a first electrode of the first transistor is connected to the first power terminal, a first electrode of the second transistor is connected to the second power terminal, and a second electrode of the first transistor and a second electrode of the second transistor are each connected to the output terminal of the first inversion unit; and wherein the second inversion unit comprises a third transistor and a fourth transistor, a gate of the third transistor and a gate of the fourth transistor are each connected to the output terminal of the storage module, a first electrode of the third transistor is connected to the first power terminal, a first electrode of the fourth transistor is connected to the second power terminal, and a second electrode of the third transistor and a second electrode of the fourth transistor are each connected to the output terminal of the second inversion unit; wherein a channel type of the first transistor is opposite to a channel type of the second transistor, a channel type of the third transistor is opposite to a channel type of the fourth transistor, and the channel type of the first transistor is the same as the channel type of the third transistor; the second transistor and the fourth transistor are each an n-type transistor; and the second transistor and the fourth transistor each comprise a second gate, and the second gate of the second transistor and the second gate of the fourth transistor are each connected to a third power terminal.

4 . The gate driving circuit according to claim 3 , further comprising a transmission control module connected between the first node and the output terminal of the second inversion unit and configured to control whether the first node communicates with the output terminal of the second inversion unit, wherein
the transmission control module comprises a fifth transistor connected between the first node and the output terminal of the second inversion unit, and a gate of the fifth transistor is connected to a second clock terminal; and the transmission control module comprises a sixth transistor connected between the first node and the output terminal of the second inversion unit, and a gate of the sixth transistor is connected to a first clock terminal; a signal connected to the first clock terminal and a signal connected to the second clock terminal are mutually inverse signals, and a channel type of the fifth transistor is opposite to a channel type of the sixth transistor; the sixth transistor is an n-type transistor; and the sixth transistor comprises a second gate, and the second gate of the sixth transistor is connected to the third power terminal.

5 . The gate driving circuit according to claim 3 , wherein the input module comprises a seventh transistor connected between the signal input terminal and the first node, and a gate of the seventh transistor is connected to a first clock terminal; and
the input module further comprises an eighth transistor connected between the signal input terminal and the first node, and a gate of the eighth transistor is connected to a second clock terminal; a signal connected to the first clock terminal and a signal connected to the second clock terminal are mutually inverse signals, and a channel type of the seventh transistor is opposite to a channel type of the eighth transistor; the eighth transistor is an n-type transistor; and the eighth transistor comprises a second gate, and the second gate of the eighth transistor is connected to the third power terminal.

6 . The gate driving circuit according to claim 2 , wherein the output module comprises a ninth transistor and a tenth transistor, a gate of the ninth transistor and a gate of the tenth transistor are each connected to the output terminal of the storage module, a first electrode of the ninth transistor is connected to a first power terminal, a first electrode of the tenth transistor is connected to a second power terminal, and a second electrode of the ninth transistor and a second electrode of the tenth transistor are each connected to the signal output terminal of the gate driving circuit;
wherein a channel type of the ninth transistor is opposite to a channel type of the tenth transistor; the tenth transistor is an n-type transistor; and the tenth transistor comprises a second gate, and the second gate of the tenth transistor is connected to a third power terminal.

7 . The gate driving circuit according to claim 3 , wherein a potential connected to the first power terminal is higher than a potential connected to the second power terminal, a potential connected to the third power terminal is lower than or equal to the potential connected to the second power terminal.

8 . A driving method of a gate driving circuit, applied to the gate driving circuit according to claim 1 and comprising:
in a first working mode, controlling the input module to be turned on, wherein the input module transmits a potential of the signal input terminal to the first node, and the storage module controls a potential of the output terminal of

Assignees

• Kunshan Govisionox Optoelectronics Co Ltd

Inventors

• Guo Enqing
• Gai Cuili
• Li Junfeng
• Pan Kangguan
• Cheng Yun

Classifications

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• G09G3/32 Primary

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title