Memory systems and operating methods thereof and memory controllers

Patent metadata

Field	Value
Publication number	US-2025165146-A1
Application number	US-202418605527-A
Country	US
Kind code	A1
Filing date	Mar 14, 2024
Priority date	Nov 22, 2023
Publication date	May 22, 2025
Grant date	—

Abstract

An example memory system is provided and includes a memory device and a memory controller. The memory controller includes a buffer and supports a host performance boost mode. The memory controller is configured to: back up the data related to the host performance boost mode in the first memory area of the buffer to a second memory area, in response to the memory controller entering the power-saving mode; the first memory area is in a power-down state when the memory controller being in the power-saving mode, and the second memory area is able to retain the data stored in the second memory area when the memory controller is in the power-saving mode; restore the data related to the host performance boost mode in the second memory area to the first memory area, in response to exiting the power-saving mode.

First claim

What is claimed is:

1 . A memory system, comprising:
a memory device; and a memory controller, which is coupled to the memory device, and includes a buffer and supports a host performance boost mode, and the memory controller is configured to:
back up data related to the host performance boost mode in a first memory area of the buffer to a second memory area, in response to the memory controller entering a power-saving mode, wherein the first memory area is in a power-down state when the memory controller being in the power-saving mode, and the second memory area is able to retain the data stored in the second memory area when the memory controller is in the power-saving mode; and
restore the data related to the host performance boost mode in the second memory area to the first memory area, in response to exiting the power-saving mode.

2 . The memory system of claim 1 , wherein the second memory area includes an area in the buffer that is in a non-power-down state when the memory controller being in the power-saving mode, or a portion of areas in the memory device.

3 . The memory system of claim 1 , wherein the memory controller is further configured to:
back up the data related to the host performance boost mode in the first memory area to an area in the buffer that is in a non-power-down state when the memory controller being in the power-saving mode, in the case that capacity of the area in the buffer that is in the non-power-down state when the memory controller being in the power-saving mode is greater than or equal to capacity required to store the data related to the host performance boost mode; and back up the data related to the host performance boost mode in the first memory area to a portion of areas in the memory device, in the case that the capacity of the area in the buffer that is in the non-power-down state when the memory controller being in the power-saving mode is less than the capacity required to store the data related to the host performance boost mode.

4 . The memory system of claim 1 , wherein the memory controller is configured to:
compress the data related to the host performance boost mode in the first memory area; and store the compressed data related to the host performance boost mode into the second memory area.

5 . The memory system of claim 4 , wherein the memory controller is configured to:
decompress the compressed data related to the host performance boost mode stored in the second memory area, in response to exiting the power-saving mode; and store the decompressed data related to the host performance boost mode into the first memory area.

6 . The memory system of claim 1 , wherein the memory controller is configured to:
generate a data mapping table which includes a mapping relationship between a first address and a second address, wherein the first address is an address of the data related to the host performance boost mode in the first memory area before being backed up to the second memory area, and the second address is an address of the data related to the host performance boost mode in the second memory area after being backed up to the second memory area; acquire the data related to the host performance boost mode stored at the second address in the second memory area, in response to exiting the power-saving mode; and restore the data related to the host performance boost mode in the second memory area to the first address in the first memory area according to the data mapping table.

7 . The memory system of claim 1 , wherein the memory controller is configured to:
enter the power-saving mode after backing up the data related to the host performance boost mode in the first memory area of the buffer to the second memory area.

8 . The memory system of claim 1 , wherein the data related to the host performance boost mode comprises: a list of areas for the host performance boost mode, a list of sub-areas for the host performance boost mode and a bitmap of dirty units.

9 . The memory system of claim 1 , wherein the memory system comprises one of a memory card, solid state disk, and general purpose flash memory.

10 . A method for operating a memory system, comprising:
backing up data related to a host performance boost mode in a first memory area of a buffer in a memory controller to a second memory area, in response to the memory controller entering a power-saving mode, wherein the first memory area is in a power-down state when the memory controller being in the power-saving mode, and the second memory area is able to retain the data stored in the second memory area when the memory controller is in the power-saving mode; and restoring the data related to the host performance boost mode in the second memory area to the first memory area, in response to exiting the power-saving mode.

11 . The method of claim 10 , wherein the second memory area includes an area in the buffer that is in a non-power-down state when the memory controller being in the power-saving mode, or a portion of areas in a memory device.

12 . The method of claim 10 , wherein backing up data related to a host performance boost mode in a first memory area of a buffer in a memory controller to a second memory area comprises:
backing up the data related to the host performance boost mode in the first memory area to an area in the buffer that is in a non-power-down state when the memory controller being in the power-saving mode, in the case that capacity of the area in the buffer that is in the non-power-down state when the memory controller being in the power-saving mode is greater than or equal to capacity required to store the data related to the host performance boost mode; and backing up the data related to the host performance boost mode in the first memory area to a portion of areas in a memory device, in the case that the capacity of the area in the buffer that is in the non-power-down state when the memory controller being in the power-saving mode is less than the capacity required to store the data related to the host performance boost mode.

13 . The method of claim 10 , wherein backing up the data related to the host performance boost mode in the first memory area of the buffer in the memory controller to a second memory area comprises:
compressing the data related to the host performance boost mode in the first memory area; and storing the compressed data related to the host performance boost mode into the second memory area.

14 . The method of claim 13 , wherein restoring the data related to the host performance boost mode in the second memory area to the first memory area, in response to exiting the power-saving mode comprises:
decompressing the compressed data related to the host performance boost mode stored in the second memory area, in response to exiting the power-saving mode; and storing the decompressed data related to the host performance boost mode into the first memory area.

15 . The method of claim 10 , wherein restoring the data related to the host performance boost mode in the second memory area to the first memory area, in response to exiting the power-saving mode comprises:
generating a data mapping table which includes a mapping relationship between a first address and a second address, wherein the first address is an address of the data related to the host performance boost mode in the first memory area before being backed up to the second memory area, and the second address is an address of the data related to the host performance boost mode in the second memory area after being backed up to the second memory area; acquiring dat

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Fu Hai
• Duan Guiyuan

Classifications

• G06F11/1441

  Resetting or repowering · CPC title

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0629

  Configuration or reconfiguration of storage systems · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0622

  in relation to access · CPC title