Display device

Patent metadata

Field	Value
Publication number	US-2025160163-A1
Application number	US-202418941326-A
Country	US
Kind code	A1
Filing date	Nov 8, 2024
Priority date	Nov 9, 2023
Publication date	May 15, 2025
Grant date	—

Abstract

Disclosed is a display device which includes a first substrate including a fan-out wiring part, a second substrate facing the first substrate, and a sealant coupling the first and second substrates. The fan-out wiring part includes first and second fan-out lines, first and second connecting lines. The first fan-out line is disposed in a non-sealing area and includes a first gate wiring layer and a third gate wiring layer. The second fan-out line is disposed in the non-sealing area and includes a second gate wiring layer having a lower sheet resistance. The first connecting line is disposed in a sealing area and connected to the first fan-out line. The second connecting line is disposed in the sealing area and connected to the second fan-out line. Each of the first and second connecting lines includes one of the first and third gate wiring layers.

First claim

What is claimed is:

1 . A display device comprising:
a first substrate including a plurality of pixels disposed in a display region and a fan-out wiring part disposed in a peripheral region adjacent to the display region; a second substrate facing the first substrate; and a sealant disposed in a sealing area of the peripheral region, the sealant coupling the first and second substrates, wherein the fan-out wiring part includes:
a first fan-out line disposed in a first non-sealing area of the peripheral region, the first fan-out line including a first gate wiring layer and a third gate wiring layer disposed on the first gate wiring layer and connected to the first gate wiring layer, the first non-sealing area not overlapping the sealant;
a second fan-out line disposed in the first non-sealing area, the second fan-out line including a second gate wiring layer having a lower sheet resistance than sheet resistances of the first and third gate wiring layers;
a first connecting line disposed in the sealing area and connected to the first fan-out line, the first connecting line including at least one of the first gate wiring layer and the third gate wiring layer; and
a second connecting line disposed in the sealing area and connected to the second fan-out line, the second connecting line including at least one of the first gate wiring layer and the third gate wiring layer.

2 . The display device of claim 1 , wherein the first, second, and third gate wiring layers are disposed on different insulating layers, respectively.

3 . The display device of claim 1 , wherein
each of the first and third gate wiring layers is a single-layer, and the second gate wiring layer is a multi-layer in which a plurality of metal layers are sequentially stacked each other.

4 . The display device of claim 3 , wherein
at least one of the plurality of metal layers includes aluminum, and the second gate wiring layer does not overlap the sealant in plan view.

5 . The display device of claim 1 , wherein the first and second connecting lines include different gate wiring layers.

6 . The display device of claim 5 , wherein
the first connecting line includes the first gate wiring layer, and the second connecting line includes the third gate wiring layer.

7 . The display device of claim 1 , further comprising:
a driver chip mounted on the first substrate, wherein the first substrate further includes data lines disposed in the display region and connected to the plurality of pixels, and the fan-out wiring part connects the driver chip and the data lines.

8 . The display device of claim 7 , wherein
the fan-out wiring part further includes:
a third fan-out line disposed in a second non-sealing area of the peripheral region, the third fan-out line including the first gate wiring layer and the third gate wiring layer, the second non-sealing area not overlapping the sealant and disposed between the sealing area and the driver chip; and
a fourth fan-out line disposed in the second non-sealing area, the fourth fan-out line including the second gate wiring layer.

9 . The display device of claim 8 , wherein
the third fan-out line is connected to the first connecting line, and the fourth fan-out line is connected to the second connecting line.

10 . The display device of claim 8 , wherein
the third fan-out line is connected to the second connecting line, and the fourth fan-out line is connected to the first connecting line.

11 . The display device of claim 7 , wherein
the fan-out wiring part further includes:
a third fan-out line disposed in a second non-sealing area of the peripheral region, the third fan-out line including a first data wiring layer, the second non-sealing area not overlapping the sealant and disposed between the sealing area and the driver chip; and
a fourth fan-out line disposed in the second non-sealing area, the fourth fan-out line including a second data wiring layer.

12 . The display device of claim 11 , wherein the first data wiring layer and the second data wiring layer are disposed on different insulating layers, respectively.

13 . The display device of claim 12 , wherein the first data wiring layer and the second data wiring layer include a same material.

14 . The display device of claim 11 , wherein
the first and second data wiring layers have a lower sheet resistance than sheet resistances of the first, second, and third gate wiring layers, and the third and fourth fan-out lines have a smaller width than widths of the first and second fan-out lines.

15 . A display device comprising:
a first substrate including a plurality of pixels disposed in a display region and a fan-out wiring part disposed in a peripheral region adjacent to the display region; a second substrate facing the first substrate; and a sealant disposed in a sealing area of the peripheral region, the sealant being coupling the first and second substrates, wherein the fan-out wiring part includes:
a first fan-out line disposed in a first non-sealing area of the peripheral region, the first fan-out line including one of a second gate wiring layer, a first data wiring layer, and a second data wiring layer, the first non-sealing area not overlapping the sealant and disposed between the sealing area and the display region;
a second fan-out line disposed in the first non-sealing area, the second fan-out line including one of the second gate wiring layer, the first data wiring layer, and the second data wiring layer;
a first connecting line disposed in the sealing area and connected to the first fan-out line, the first connecting line including at least one of a first gate wiring layer and a third gate wiring layer; and
a second connecting line disposed in the sealing area and connected to the second fan-out line, the second connecting line including at least one of the first gate wiring layer and the third gate wiring layer,
the first, second, and third gate wiring layers and the first and second data wiring layers are disposed on different insulating layers, and the second gate wiring layer and the first and second data wiring layers have a lower sheet resistance than sheet resistances of the first and third gate wiring layers.

16 . The display device of claim 15 , wherein the first and second connecting lines include different gate wiring layers, respectively.

17 . The display device of claim 16 , wherein
the first connecting line includes the first gate wiring layer, and the second connecting line includes the third gate wiring layer.

18 . The display device of claim 15 , further comprising:
a driver chip mounted on the first substrate, wherein the first substrate further includes data lines disposed in the display region and connected to the plurality of pixels, and the fan-out wiring part connects the driver chip and the data lines.

19 . The display device of claim 18 , wherein the fan-out wiring part further includes:
a third fan-out line disposed in a second non-sealing area of the peripheral region, the third fan-out line including one of the first and second data wiring layers, the second non-sealing area not overlapping the sealant and disposed between the sealing area and the driver chip; and a fourth fan-out line disposed in the second non-sealing area, the fourth fan-out line including one of the first and second data wiring layers.

20 . The display device of claim 19 , wherein
each of the first, second, third, and fourth fan-out lines includes th

Assignees

• Samsung Display Co Ltd

Inventors

• Choi Junwon
• Bang Hyun-Chol

Classifications

• H10K59/8722 Primary

  Peripheral sealing arrangements, e.g. adhesives, sealants · CPC title

• H10K71/50

  Forming devices by joining two substrates together, e.g. lamination techniques · CPC title

• H10K59/129

  Chiplets · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10K77/10

  Substrates, e.g. flexible substrates · CPC title