Integrated circuit device

Patent metadata

Field	Value
Publication number	US-2025157921-A1
Application number	US-202418740739-A
Country	US
Kind code	A1
Filing date	Jun 12, 2024
Priority date	Nov 9, 2023
Publication date	May 15, 2025
Grant date	—

Abstract

Provided is an integrated circuit device with reduced line margins. The integrated circuit device includes an active area on a substrate, a channel area in the active area, a gate line that extends around the channel area, a plurality of first upper lines that electrically connect the channel area and the gate line to each other, a plurality of first lower lines of a side of the substrate, and a second lower wiring line on a side of the plurality of first lower lines that is opposite the substrate. The plurality of first lower lines includes a jog pattern line and an island pattern line that is spaced apart from the jog pattern line, and the island pattern line is electrically connected to the second lower wiring line by a lower contact.

First claim

What is claimed is:

1 . An integrated circuit device comprising:
a fin-type active area on a substrate; a channel area in the fin-type active area; a gate line that extends around the channel area; a plurality of first upper lines that electrically connect the channel area and the gate line to each other; a plurality of first lower lines below the substrate; and a second lower wiring line below the plurality of first lower lines, wherein the plurality of first lower lines comprise a jog pattern line and an island pattern line that is spaced apart from the jog pattern line, and wherein the island pattern line is electrically connected to the second lower wiring line by a lower contact.

2 . The integrated circuit device of claim 1 , wherein the jog pattern line extends in a first direction that is perpendicular to a second direction in which the plurality of first upper lines extend.

3 . The integrated circuit device of claim 2 , wherein the lower contact overlaps the island pattern line in a third direction that intersects the first direction and the second direction,
wherein the lower contact is, in a plan view, included in an area formed by the island pattern line.

4 . The integrated circuit device of claim 1 , wherein the jog pattern line is electrically connected to a gate of a transistor, and
wherein the island pattern line is electrically connected to a source region of the transistor.

5 . The integrated circuit device of claim 1 , wherein the jog pattern line comprises a first jog pattern line in a first unit cell,
wherein the first jog pattern line is origin-symmetric with respect to a second jog pattern line, which is in a second unit cell that is adjacent to the first unit cell, and wherein the first jog pattern line is origin-symmetric with respect to the island pattern line.

6 . The integrated circuit device of claim 1 , wherein the island pattern line overlaps the second lower wiring line in plan view.

7 . The integrated circuit device of claim 1 , wherein a voltage applied to some of the first upper lines and a voltage applied to the island pattern line and the second lower wiring line are different from each other.

8 . The integrated circuit device of claim 1 , wherein the plurality of first upper lines comprise three first upper lines per unit cell.

9 . The integrated circuit device of claim 1 , wherein six or more transistors are included per unit cell.

10 . The integrated circuit device of claim 1 , wherein the jog pattern line and the island pattern line are electrically isolated from each other.

11 . The integrated circuit device of claim 1 , wherein the jog pattern line is spaced apart from the second lower wiring line.

12 . The integrated circuit device of claim 1 , wherein the second lower wiring line extends in a same direction as a direction in which the plurality of first upper lines extend.

13 . The integrated circuit device of claim 12 , wherein the second lower wiring line comprises two second lower wiring lines per unit cell.

14 . An integrated circuit device comprising:
a substrate having a front surface and a rear surface that are opposite to each other, and having a fin-type active area on the front surface, wherein the fin-type active area is adjacent a trench; source/drain regions on the fin-type active area; gate electrodes that extend across the fin-type active area; a plurality of first upper lines that are on the source/drain regions and electrically connected to the source/drain regions by at least one via; a plurality of first lower lines below the substrate; a second lower wiring line below the plurality of first lower lines, and on a side of a second island pattern line; and a third lower wiring line below the second lower wiring line, wherein the plurality of first lower lines comprise a jog pattern line and a first island pattern line that is spaced apart from the jog pattern line, wherein the first island pattern line is electrically connected to the second lower wiring line and the third lower wiring line by a first lower contact, and wherein the jog pattern line is electrically connected to the second island pattern line by the first lower contact, and is electrically connected to the third lower wiring line by a second lower contact.

15 . The integrated circuit device of claim 14 , wherein the third lower wiring line and the jog pattern line extend in a first direction that is perpendicular to a second direction in which the plurality of first upper lines extend.

16 . The integrated circuit device of claim 15 , wherein the first island pattern line overlaps the second lower wiring line in a third direction that intersects the first direction the second direction, and
wherein the first lower contact overlaps the first island pattern line in the third direction and is, in a plan view, included in an area adjacent the first island pattern line.

17 . The integrated circuit device of claim 14 , wherein the jog pattern line is spaced apart from the second lower wiring line.

18 . An integrated circuit device comprising:
a plurality of nanosheets; a plurality of gate lines; a plurality of transistors at respective intersections of ones of the plurality of nanosheets and ones of the plurality of gate lines, the plurality of transistors comprising at least a portion included in a static random access memory (SRAM); a plurality of first upper lines in a first layer above a second layer of the plurality of transistors, and electrically connected to a source/drain region of at least one of the plurality of transistors by at least one via; a plurality of first lower lines on a third layer that is below the second layer of the plurality of transistors; and a second lower line pattern on a fourth layer that is below the third layer of the plurality of first lower lines, wherein the second lower line pattern comprises a wiring line of at least one layer, and when the wiring line comprises two or more layers that are in different layers from each other, wherein the plurality of first lower lines comprise a jog pattern line and an island pattern line that is spaced apart from the jog pattern line, and wherein the island pattern line is electrically connected to the second lower line pattern by a lower contact.

19 . The integrated circuit device of claim 18 , wherein the jog pattern line extends in a first direction that is perpendicular to a second direction in which the plurality of first upper lines extend, and is spaced apart from the second lower line pattern.

20 . The integrated circuit device of claim 19 , wherein the lower contact overlaps the island pattern line in a third direction that is perpendicular to the first direction and the second direction, and is, in a plan view, included in an area adjacent the island pattern line.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jeewoong
• Lee Seunghun
• Lee Kyowook
• Cho Keunhwi

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title