Memory with deferred fractional row activation

Patent metadata

Field	Value
Publication number	US-2025157503-A1
Application number	US-202418956309-A
Country	US
Kind code	A1
Filing date	Nov 22, 2024
Priority date	Jul 27, 2011
Publication date	May 15, 2025
Grant date	—

Abstract

Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

First claim

1 - 20 . (canceled)

21 . A method of operation within a memory control component, the method comprising:
outputting a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and after outputting the row command and the first address, outputting a first column command and a second address to the DRAM component, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the DRAM component to:
transfer a first sub-row of data, including the first column of data, from the first sub-row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers; and
charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command.

22 . The method of claim 21 wherein outputting the first column command and the second address to the DRAM component comprises outputting the first column command and the second address to the DRAM component a second predetermined time after outputting the row command and the first address.

23 . The method of claim 22 wherein outputting the first column command and the second address to the DRAM component comprises outputting, over a sequence of one or more command/address transmit intervals defined by one or more respective transitions of a first clock signal, a packetized command/address value constituted at least in part by the first column command and the second address.

24 . The method of claim 23 wherein the first predetermined time elapses over an integer number of cycles of the first clock signal.

25 . The method of claim 21 wherein outputting the first column command and second address to the DRAM component comprises outputting a command/address value having one or more bits in respective predetermined states to specify that the DRAM component is to charge the bit lines to the precharge voltage level after the first predetermined time elapses.

26 . The method of claim 21 wherein the first column command additionally instructs the DRAM component to clear the first sub-row of data from the first set of sense amplifiers concurrently with charging the bit lines to the precharge voltage level.

27 . The method of claim 21 wherein the DRAM component comprises data interface circuitry coupled to the first set of sense amplifiers and other sets of sense amplifiers via column multiplexing circuitry, and wherein the first column command additionally instructs the DRAM component to convey, via the column multiplexing circuitry, the first column of data from the first set of sense amplifiers to the data interface circuitry for transmission to the memory control component, the first column of data constituting read data requested by the first column command.

28 . The method of claim 21 further comprising transmitting write data to the DRAM component and wherein the first column command additionally instructs the DRAM component to receive the write data and store the write data within the first set of sense amplifiers, overwriting the first column of data therein.

29 . The method of claim 21 wherein outputting the first column command and the second address comprises outputting a command/address packet including the first column command and the second address and wherein the second address comprises (i) a sub-row address bit-field that specifies, as the first sub-row of storage cells, one of a plurality of sub-rows of storage cells that collectively constitute the first row of storage cells, and (ii) a column-offset bit-field that specifies, within the first sub-row of storage cells, a subset of storage cells containing the first column of data.

30 . The method of claim 29 further wherein the first address comprises (i) a bank address bit-field that specifies a first storage bank from among a plurality of storage banks within the DRAM component and (ii) a row-address bit-field that specifies, as the first row of storage cells, one of a plurality of rows of storage cells within the first storage bank.

31 . A memory control component comprising:
a first signaling interface; and control circuitry to output via the first signaling interface:
a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and
a first column command and a second address to the DRAM component after outputting the row command and the first address, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the DRAM component to:
transfer a first sub-row of data, including the first column of data, from the first sub-row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers; and
charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command.

32 . The memory control component of claim 31 wherein the control circuitry to output the first column command and the second address to the DRAM component comprises signaling circuitry to output the first column command and the second address to the DRAM component a second predetermined time after outputting the row command and the first address.

33 . The memory control component of claim 32 wherein the signaling circuitry to output the first column command and the second address to the DRAM component comprises synchronous signaling circuitry to output, over a sequence of one or more command/address transmit intervals defined by one or more respective transitions of a first clock signal, a packetized command/address value constituted at least in part by the first column command and the second address.

34 . The memory control component of claim 33 wherein the first predetermined time elapses over an integer number of cycles of the first clock signal.

35 . The memory control component of claim 31 wherein the control circuitry to output the first column command and second address to the DRAM component comprises circuitry to output a command/address value having one or more bits in respective predetermined states to specify that the DRAM component is to charge the bit lines to the precharge voltage level after the first predetermined time elapses.

36 . The memory control component of claim 31 wherein the DRAM component comprises data interface circuitry coupled to the first set of sense amplifiers and other sets of sense amplifiers via column multiplexing circuitry, and wherein the first column command additionally instructs the DRAM component to convey, via the column multiplexing circuitry, the first column of data from the first set of sense amplifiers to the data interface circuitry for transmission to the memory control component, the first column of data constituting read data requested by the first column command.

37 . The memory control component of claim 31 wherein the first signaling interface comprises a data interface to transmit write data to the DRAM component and wherein the first column command additionally

Assignees

• Rambus Inc

Inventors

• Harris James E
• Vogelsang Thomas
• Ware Frederick A
• Shaeffer Ian P

Classifications

• G11C8/10

  Decoders · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C7/065

  Differential amplifiers of latching type · CPC title