Display substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-2025157396-A1
Application number	US-202519021203-A
Country	US
Kind code	A1
Filing date	Jan 15, 2025
Priority date	Sep 11, 2020
Publication date	May 15, 2025
Grant date	—

Abstract

A display substrate and a display apparatus are provided. The display substrate includes a base substrate; sub-pixels arranged in an array and on the base substrate; data line groups on the base substrate; each data line group includes data lines, each of which is connected to one column of sub-pixels; data selectors on the base substrate and connected to the data line groups in a one-to-one correspondence; data lines in a same data line group are connected to a same data selector; and data selection signal lines, wherein different data selection signal lines output different data selection signals; and different data lines connected to a same data selector correspond to different data selection signal lines, respectively. The display panel provided may effectively reduce the resistance on the data selection signal lines, thereby reducing the delay of the data selection signals and further improving the charging uniformity of sub-pixels.

First claim

What is claimed is:

1 . A display substrate, comprising:
a base substrate; a plurality of sub-pixels arranged in an array and on the base substrate; a plurality of data line groups on the base substrate; wherein each of the plurality of data line groups comprises a plurality of data lines, and each of the plurality of data lines is connected to one column of sub-pixels; a plurality of data selectors on the base substrate and connected to the plurality of data line groups in a one-to-one correspondence; wherein data lines in a same data line group are connected to a same data selector; and a plurality of data selection signal lines, wherein different data selection signal lines output different data selection signals; and different data lines connected to a same data selector correspond to different data selection signal lines, respectively; and each of the data selection signal lines comprises a plurality of signal sub-lines.

2 . The display substrate of claim 1 , wherein the plurality of signal sub-lines of a same data selection signal line transmit a same data selection signal.

3 . The display substrate of claim 1 , further comprising a plurality of connectors, wherein
the plurality of connectors are arranged sequentially along a first direction; and each of the plurality of signal sub-lines extends along the first direction, and has two ends which are connected to two outermost connectors in the first direction of the plurality of connectors.

4 . The display substrate of claim 1 , further comprising a plurality of connectors, wherein
the plurality of connectors are arranged sequentially along a first direction; and each of the plurality of signal sub-lines extends along the first direction, and is connected to each of the plurality of connector through pins on two opposite sides of the connector in the first direction.

5 . The display substrate of claim 1 , wherein a width of each of the plurality of signal sub-lines is in a range of 60 μm to 130 μm.

6 . The display substrate of claim 4 , wherein for the signal sub-lines connected to a same connector, a position close to the pin refers to as a proximal end, and a position away from the pin refers to as a distal end, and a difference between a charging rate of a sub-pixel connected to a data line corresponding to the proximal end and a charging rate of a sub-pixel connected to a data line corresponding to the distal end is less than or equal to 15%.

7 . The display substrate of claim 6 , wherein the charging rate of the sub-pixel connected to the data line corresponding to the proximal end and the charging rate of the sub-pixel connected to the data line corresponding to the distal end is greater than or equal to 90%.

8 . The display substrate of claim 6 , wherein a rising edge time and a falling edge time of a charging waveform of the signal sub-line at the proximal end each are in a range of 50 nm to 120 ns; and a rising edge time and a falling edge time of a charging waveform of the signal sub-line at the distal end each are in a range of 50 ns to 120 ns.

9 . The display substrate of claim 1 , wherein each of the plurality of data line groups comprises a plurality of data lines, and
in the plurality of data lines of a same data line group, any two adjacent data lines are spaced from each other by at least one of the plurality of data lines; or each of the plurality of data line groups comprises adjacent ones of the plurality of data lines.

10 . The display substrate of claim 1 , wherein the display substrate comprises a first data selection signal line and a second data selection signal line;
the first data selection signal line comprises four first signal sub-lines sequentially corresponding to data lines, which are connected to odd columns of sub-pixels, in the plurality of data line groups connected to the plurality of data selectors; and the second data selection signal line comprises four second signal sub-lines sequentially corresponding to data lines, which are connected to even columns of sub-pixels, in the plurality of data line groups connected to the plurality of data selectors.

11 . The display substrate of claim 9 , wherein each of the plurality of data line groups comprises two data lines which are spaced from each other by another data line of the plurality of data lines, or each of the plurality of data line groups comprises two adjacent data lines.

12 . The display substrate of claim 1 , wherein each of the plurality of data selectors comprises a plurality of transistors;
the number of the transistors in each of the plurality of data selectors is the same as the number of the data lines in each of the plurality of data line groups; and in each of the plurality of data selectors, control electrodes of the transistors are connected to the corresponding data selection signal lines, respectively; first electrodes of the transistors are connected to different data lines, respectively, and second electrodes of the transistors are connected together to receive data voltages.

13 . The display substrate of claim 12 , wherein each of the plurality of data selectors comprises a first transistor and a second transistor;
a first electrode of the first transistor in the data selector is connected to a corresponding data line, and a first electrode of the second transistor in the data selector is connected to a corresponding data line; the display substrate comprises a first data selection signal line and a second data selection signal line, the first data selection signal line is connected to control electrodes of the first transistors in the plurality of data selectors; the second data selection signal line is connected to control electrodes of the second transistors in the plurality of data selectors; and the second electrodes of the first transistor and the second transistor in each of the plurality of data selectors are connected together.

14 . The display substrate of claim 1 , wherein the display substrate comprises a first data selection signal line and a second data selection signal line;
the first data selection signal line comprises two first signal sub-lines sequentially corresponding to data lines, which are connected to odd columns of sub-pixels, in the plurality of data line groups connected to the plurality of data selectors; and the second data selection signal line comprises two second signal sub-lines sequentially corresponding to data lines, which are connected to even columns of sub-pixels, in the plurality of data line groups connected to the plurality of data selectors.

15 . The display substrate of claim 9 , wherein a first sub-pixel, a second sub-pixel and a third sub-pixel arranged in sequence along a first direction form one pixel unit; pixel units in a same column are connected to a same data line group; each data line group comprises three adjacent data lines connected to one column of first sub-pixels, one column of second sub-pixels and one column of third sub-pixels, respectively;
the display substrate comprises a first data selection signal line, a second data selection signal line and a third data selection signal line; the first data selection signal line comprises two first signal sub-lines sequentially corresponding to data lines, which are connected to the first sub-pixels, in data line groups connected to the plurality of data selectors; the second data selection signal line comprises two second signal sub-lines sequentially corresponding to data lines, which are connected to the second sub-pixels, in data line groups connected to the plurality of data selectors;

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zhang Jian
• Wang Zhen
• Wang Deshuai
• Zhang Han
• Yan Wei
• Sun Jian

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

• G09G2310/0275

  Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current · CPC title

• G09G2370/08

  Details of image data interface between the display device controller and the data line driver circuit · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title