Voltage regulators

Patent metadata

Field	Value
Publication number	US-2025155911-A1
Application number	US-202418756948-A
Country	US
Kind code	A1
Filing date	Jun 27, 2024
Priority date	Nov 10, 2023
Publication date	May 15, 2025
Grant date	—

Abstract

A voltage regulator includes a pass transistor generating an output voltage in response to a gate voltage, and an error amplifier circuit outputting the gate voltage. The error amplifier circuit includes a first input terminal receiving a first reference voltage level from a reference voltage generator, a second input terminal receiving a second reference voltage level from the reference voltage generator, a third input terminal receiving a first voltage level of a first end of a target circuit, a fourth input terminal receiving a second voltage level of a second end of the target circuit, and an output terminal that outputs the gate voltage generated based on the first reference voltage level, the second reference voltage level, the first voltage level, and the second voltage level. A potential difference of the first voltage level and the second voltage level is an operating voltage of the target circuit.

First claim

What is claimed is:

1 . A voltage regulator comprising:
at least one pass transistor configured to generate an output voltage based on a gate voltage; and an error amplifier circuit configured to output the gate voltage, wherein the error amplifier circuit includes:
a first input terminal configured to receive a first reference voltage level from a reference voltage generator;
a second input terminal configured to receive a second reference voltage level from the reference voltage generator;
a third input terminal configured to receive a first voltage level of a first end of a target circuit;
a fourth input terminal configured to receive a second voltage level of a second end of the target circuit; and
an output terminal, wherein the error amplifier circuit is configured to generate the gate voltage based on the first reference voltage level, the second reference voltage level, the first voltage level, and the second voltage level, and to output the gate voltage at the output terminal, and
wherein a potential difference between the first voltage level and the second voltage level is an operating voltage of the target circuit.

2 . The voltage regulator of claim 1 , wherein the operating voltage of the target circuit is smaller than the output voltage.

3 . The voltage regulator of claim 1 , wherein a potential difference between the first reference voltage level and the second reference voltage level is a reference voltage.

4 . The voltage regulator of claim 3 , wherein the operating voltage matches the reference voltage.

5 . The voltage regulator of claim 1 , wherein the error amplifier circuit is configured to:
sum the first reference voltage level and the first voltage level, to obtain a first signal; sum the second reference voltage level and the second voltage level, to obtain a second signal; compare the first signal and the second signal, to obtain a comparison result; and generate the gate voltage based on the comparison result.

6 . The voltage regulator of claim 1 , further comprising:
a header transistor connected between the at least one pass transistor and the first end of the target circuit and configured to operate in response to a first power gating voltage; and a footer transistor connected between the second end of the target circuit and a ground node and configured to operate in response to a second power gating voltage.

7 . The voltage regulator of claim 1 , wherein the at least one pass transistor includes:
a first transistor connected between a first node and a second node and configured to operate in response to the gate voltage; a second transistor including a gate connected to the second node and connected between the first node and a power node; and a third transistor connected between the second node and a ground node and configured to operate in response to a bias voltage, and wherein the first node and the target circuit are connected through a circuit line.

8 . The voltage regulator of claim 1 , wherein the at least one pass transistor includes a p-type metal-oxide-semiconductor field-effect-transistor connected to an output node and configured to operate in response to the gate voltage, and
wherein the output node is connected to the first end of the target circuit through a circuit line.

9 . The voltage regulator of claim 1 , wherein the error amplifier circuit includes:
a first transistor connected between a first node and a third node and configured to operate in response to the first reference voltage level; a second transistor connected between a second node and a fourth node and configured to operate in response to the second reference voltage level; a third transistor connected between the first node and a fifth node and configured to operate in response to the first voltage level; a fourth transistor connected between the second node and a sixth node and configured to operate in response to the second voltage level; a fifth transistor connected between a power node and the third node and configured to operate in response to a bias voltage; a sixth transistor connected between the power node and the fourth node and configured to operate in response to the bias voltage; a seventh transistor connected between the power node and the fifth node and configured to operate in response to the bias voltage; an eighth transistor connected between the power node and the sixth node and configured to operate in response to the bias voltage; and an output stage circuit configured to generate the gate voltage based on a first signal at the first node and a second signal at the second node.

10 . The voltage regulator of claim 9 , wherein the error amplifier circuit includes:
a first degeneration resistor connected between the third node and the sixth node; and a second degeneration resistor connected between the fourth node and the fifth node.

11 . The voltage regulator of claim 10 , wherein a first resistance magnitude of the first degeneration resistor matches a second resistance magnitude of the second degeneration resistor.

12 . A voltage regulator configured to generate an output voltage, comprising:
an error amplifier circuit configured to generate a gate voltage based on a first reference voltage level, a second reference voltage level, a first voltage level of a first end of a target circuit, and a second voltage level of a second end of the target circuit; and at least one pass transistor configured to generate the output voltage in response to the gate voltage, wherein the first end of the target circuit is connected to the pass transistor through a circuit line, wherein a potential difference between the first reference voltage level and the second reference voltage level is a reference voltage, and wherein a potential difference between the first voltage level and the second voltage level is an operating voltage of the target circuit.

13 . The voltage regulator of claim 12 , wherein the output voltage is greater than the operating voltage.

14 . The voltage regulator of claim 12 , wherein the operating voltage matches the reference voltage.

15 . The voltage regulator of claim 12 , further comprising:
a plurality of target circuits connected between an output node of the at least one pass transistor and a circuit ground, a first switch circuit connected between first ends of the target circuits and the error amplifier circuit and configured to select one or more of the target circuits to be connected to the error amplifier circuit through the first switch circuit; and a second switch circuit connected between second ends of the target circuits and the error amplifier circuit and configured to select one or more of the target circuits to be connected to the error amplifier circuit through the second switch circuit, wherein a voltage level of a third node at which the error amplifier circuit and the first switch circuit are connected matches the first voltage level, and wherein a voltage level of a fourth node where the error amplifier circuit and the second switch circuit are connected matches the second voltage level.

16 . The voltage regulator of claim 12 , further comprising:
a feedback circuit connected between the first end of the target circuit and the error amplifier circuit and configured to generate a third voltage level based on the first voltage level and to provide the third voltage level to the error amplifier circuit, wherein the error amplifier circuit is configured to generate the gate voltage based on the third voltage level, and wherein the operating volt

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lim Chaekang
• Park Youngwoo
• Park Seungjin
• Byun Jindo
• Lee Seunghoon
• Choi Youngdon

Classifications

• G05F1/575 Primary

  characterised by the feedback circuit · CPC title

• G05F1/577

  for plural loads · CPC title