Display substrate, display panel and display device

Patent metadata

Field	Value
Publication number	US-2025155762-A1
Application number	US-202519024340-A
Country	US
Kind code	A1
Filing date	Jan 16, 2025
Priority date	Jul 12, 2022
Publication date	May 15, 2025
Grant date	—

Abstract

A display substrate, including: a base substrate; a plurality of data lines on the base substrate; a first insulating layer on a side of the plurality of data lines away from the base substrate; a plurality of gate lines on a side of the first insulating layer away from the plurality of data lines, where extension directions of the gate and data lines are intersected; a second insulating layer on a side of the plurality of gate lines away from the first insulating layer; and a first electrode on a side of the second insulating layer away from the plurality of gate lines, where at least a portion of an orthographic projection of the first electrode on the base substrate is within an region surrounded by orthographic projections of two adjacent data lines on the base substrate and orthographic projections of two adjacent gate lines on the base substrate.

First claim

What is claimed is:

1 . A display substrate, comprising:
a base substrate; a plurality of data lines on the base substrate; a first insulating layer on a side of a layer where the plurality of data lines are positioned away from the base substrate, wherein the first insulating layer comprises an inorganic insulating material; a plurality of gate lines a side of the first insulating layer away from the layer where the plurality of data lines are positioned, wherein an extension direction of each of the plurality of gate lines and an extension direction of each of the plurality of data lines are intersected; a second insulating layer on a side of a layer where the plurality of gate lines are positioned away from the first insulating layer, wherein the second insulating layer comprises an inorganic insulating material; and a first electrode on a side of the second insulating layer away from the layer where the plurality of gate lines are positioned, wherein at least a portion of an orthographic projection of the first electrode on the base substrate is within an region surrounded by orthographic projections of two adjacent ones of the plurality of data lines on the base substrate and orthographic projections of two adjacent ones of the plurality of gate lines on the base substrate, wherein the display substrate further comprises: a transistor, wherein a gate of the transistor is in the same layer as the data line, a first electrode and a second electrode of the transistor are in the same layer as the gate line; the gate of the transistor is electrically connected to the gate line, and the first electrode of the transistor is electrically connected to the data line; and a first transfer electrode, which is in the same layer as the first electrode; wherein the first transfer electrode is electrically connected to the gate of the transistor through a first via penetrating through the first insulating layer and the second insulating layer, and is electrically connected to the gate line through a second via penetrating through the second insulating layer.

2 . The display substrate of claim 1 , wherein an orthographic projection of a portion of each of at least a part of the plurality of data lines on the base substrate is within the orthographic projection of the first electrode on the base substrate, the first electrode comprises a plurality of slits, and a minimum distance between each of the plurality of slits and the data line in the extension direction of the gate line is greater than 1.5 μm.

3 . The display substrate of claim 1 , wherein an orthographic projection of the first via on the base substrate is within an orthographic projection of the gate of the transistor on the base substrate, an aperture of the first via in a direction away from the base substrate is gradually increased, the first via comprises a first port close to the base substrate, a length of the first port in the extension direction of the gate line is greater than or equal to 3 μm, and a width of the first port in the extension direction of the data line is greater than or equal to 6 μm, and/or
an orthographic projection of the second via on the base substrate is within the orthographic projection of the gate line on the base substrate, an aperture of the second via in the direction away from the base substrate is gradually increased, the second via comprises a second port close to the base substrate, a length of the second port in the extension direction of the gate line is greater than or equal to 3 μm, and a width of the second port in the extension direction of the data line is greater than or equal to 8 μm.

4 . The display substrate of claim 1 , wherein the gate line comprises a protrusion disposed side arranged by side with the first electrode of the transistor, the orthographic projection of the first via on the base substrate is not overlapped with an orthographic projection of the protrusion on the base substrate, and the orthographic projection of the second via on the substrate is within the orthographic projection of the protrusion on the base substrate, and
a minimum distance between the first electrode of the transistor and the protrusion is greater than or equal to 5 μm.

5 . The display substrate of claim 4 , wherein the gate line comprises a wiring portion that is integrally provided with the protrusion, a line width of the wiring portion in the extension direction of the data line is greater than or equal to 5 μm, and
the wiring portion and the protrusion form an accommodating groove, the first electrode of the transistor is in the accommodating groove.

6 . The display substrate of claim 5 , wherein the orthographic projection of the gate of the transistor on the base substrate is partially overlapped with an orthographic projection of the accommodating groove on the base substrate, and/or
wherein the first electrode of the transistor comprises a first subsection extending along the extension direction of the gate line, an orthographic projection of the first subsection on the base substrate is partially overlapped with the orthographic projection of the gate of the transistor on the base substrate, and is not overlapped with the orthographic projection of the data line on the substrate, and a distance between the first subsection and the wiring portion is greater than or equal to 5 μm, and a width of the first subsection in the extension direction of the data line is greater than or equal to 3 μm.

7 . The display substrate of claim 1 , wherein the first via and the second via are integrally provided as a first through hole, an orthographic projection of the first through hole on the base substrate is within the orthographic projection of the first transfer electrode on the base substrate, and a one-side excess distance of the orthographic projection of the first transfer electrode on the base substrate relative to the orthographic projection of the first through hole on the base substrate in the extension direction of the data line is greater than or equal to 3 μm, and/or, a one-side excess distance of the orthographic projection of the first transfer electrode on the base substrate relative to the orthographic projection of the first through hole on the base substrate in the extension direction of the gate line is greater than or equal to 3 μm, and/or
a minimum distance between the orthographic projection of the first electrode of the transistor on the base substrate and the orthographic projection of the first transfer electrode on the base substrate is greater than or equal to 3 μm.

8 . The display substrate of claim 1 , further comprising a second transfer electrode, which is in the same layer and made of the same material as the first transfer electrode;
wherein the second transfer electrode is electrically connected to the data line through a third via penetrating through the first insulating layer and the second insulating layer, and is electrically connected to the first electrode of the transistor through a fourth via penetrating through the second insulating layer.

9 . The display substrate of claim 8 , wherein the data line comprises a widened portion, an orthographic projection of the third via on the base substrate is within an orthographic projection of the widened portion on the base substrate, an aperture of the third via in a direction away from the base substrate is gradually increased, the third via comprises a third port close to the base substrate, a length of the third port in the extension direction of the gate line is greater than or equal to 6 μm, and a width of the third port in the extension direction of the data line is greater than or equal to 3 μm.

10 . The display substrat

Assignees

• Beijing Boe Display Tech Co
• Boe Technology Group Co Ltd

Inventors

• Liao Yanping
• Miao Yingmeng
• Liu Dong
• Shao Xibin
• Jiang Peng
• Chen Dongchuan
• Zhao Panhui
• Liu Jiantao
• Yang Tao
• Qu Yingying

Classifications

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/451 Primary

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title