Method of manufacturing magnetoresistive random access memory device

Patent metadata

Field	Value
Publication number	US-2025151627-A1
Application number	US-202418671519-A
Country	US
Kind code	A1
Filing date	May 22, 2024
Priority date	Nov 3, 2023
Publication date	May 8, 2025
Grant date	—

Abstract

A method of manufacturing a magnetoresistive memory device includes: forming, sequentially, a magnetic tunnel junction (MTJ) structure and a metal layer on a substrate in first and second cell regions; performing a first oxidation process on the metal layer in the first and second cell regions to form a first metal oxide layer; performing an ion implantation process on the first metal oxide layer in the first cell region to form a second metal oxide layer while the first metal oxide layer is exposed in the second cell region; and patterning the MTJ structure, the first and second metal oxide layers to form a first memory element including a first MTJ structure and the second metal oxide layer in the first cell region, and to form a second memory element including a second MTJ structure and the first metal oxide layer in the second cell region.

First claim

What is claimed is:

1 . A method of manufacturing a magnetoresistive memory device, the method comprising:
forming, sequentially, a magnetic tunnel junction structure and a metal layer on a substrate in a first cell region and a second cell region; performing a first oxidation process on the metal layer in the first cell region and the second cell region to form a first metal oxide layer; performing an ion implantation process on the first metal oxide layer in the first cell region to form a second metal oxide layer while the first metal oxide layer is exposed in the second cell region; and patterning the magnetic tunnel junction structure, the first metal oxide layer and the second metal oxide layer to form a first memory element including a first magnetic tunnel junction structure and the second metal oxide layer in the first cell region, and to form a second memory element including a second magnetic tunnel junction structure and the first metal oxide layer in the second cell region.

2 . The method of claim 1 , wherein an oxygen concentration of the second metal oxide layer is greater than an oxygen concentration of the first metal oxide layer.

3 . The method of claim 1 , wherein a peak point of an oxygen concentration of the second metal oxide layer is disposed in a region spaced apart from an upper surface of the second metal oxide layer.

4 . The method of claim 1 , wherein a peak point of an oxygen concentration of the first metal oxide layer is disposed at an upper surface of the first metal oxide layer.

5 . The method of claim 1 , wherein the ion implantation process comprises scanning the first cell region with an ion beam.

6 . The method of claim 1 , wherein the metal layer includes at least one of tantalum (Ta), ruthenium (Ru), or magnesium (Mg).

7 . The method of claim 1 , wherein the first oxidation process comprises a thermal oxidation process.

8 . The method of claim 1 , wherein the first memory element and the second memory element have different data retention characteristics and operation speeds.

9 . A method of manufacturing a magnetoresistive memory device, the method comprising:
forming, sequentially, a magnetic tunnel junction structure and a metal layer on a substrate in a first cell region and a second cell region; performing a first oxidation process on the metal layer in the first cell region and the second cell region to form a first metal oxide layer; performing a second oxidation process on the first metal oxide layer in the first cell region to form a second metal oxide layer; and patterning the magnetic tunnel junction structure and the first metal oxide layer and the second metal oxide layer to form a first memory element including a first magnetic tunnel junction structure and the second metal oxide layer in the first cell region, and to form a second memory element including a second magnetic tunnel junction structure and the first metal oxide layer in the second cell region, wherein an oxygen concentration of the first memory element is different from an oxygen concentration of the second memory element.

10 . The method of claim 9 , wherein the oxygen concentration of the second metal oxide layer is greater than the oxygen concentration of the first metal oxide layer.

11 . The method of claim 9 , wherein the first memory element and the second memory element have different electrical characteristics.

12 . The method of claim 9 , wherein the first oxidation process comprises a thermal oxidation process, and the second oxidation process comprises an ion implantation process.

13 . The method of claim 9 , wherein performing the second oxidation process comprises:
shielding the second cell region using a shadow mask mounted to equipment for performing the second oxidation process.

14 . The method of claim 9 , wherein performing the second oxidation process comprises forming a hardened first mask layer exposing the first metal oxide layer in the first cell region.

15 . The method of claim 9 , wherein performing the second oxidation process comprises:
forming a first mask layer on the first metal oxide layer in the first cell region and the second cell region; forming a second mask layer exposing the second cell region on the first mask layer; forming a hardened first mask layer by irradiating an electron beam to the first mask layer exposed in the second cell region; removing the second mask layer; removing the first mask layer from the first cell region; performing the second oxidation process; and removing the hardened first mask layer from the second cell region.

16 . The method of claim 15 , wherein the first mask layer includes a SiCN.

17 . The method of claim 9 , wherein a thickness of the second metal oxide layer is smaller than a thickness of the first metal oxide layer.

18 . A method of manufacturing a magnetoresistive memory device, the method comprising:
forming, sequentially, a magnetic tunnel junction structure and a metal layer on a substrate in a first cell region and a second cell region; performing a first oxidation process on the first cell region and the second cell region; performing, selectively, a second oxidation process on the first cell region; and patterning the magnetic tunnel junction structure to form a first magnetic tunnel junction structure in the first cell region and form a second magnetic tunnel junction structure in the second cell region, wherein a first memory element, formed in the first cell region and including the first magnetic tunnel junction structure, and a second memory element, formed in the second cell region and including the second magnetic tunnel junction structure, have different electrical characteristics.

19 . The method of claim 18 , wherein the second oxidation process is performed without a mask.

20 . The method of claim 18 , wherein the electrical characteristics of first memory element and the second memory element include at least one of different data retention characteristics or different operation speeds.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Kilho
• Kim Yongjae
• Suh Kiseok

Classifications

• H10B61/10

  comprising components having two electrodes, e.g. diodes or MIM elements · CPC title

• H10N50/80

  Constructional details · CPC title

• H10N50/01 Primary

  Manufacture or treatment · CPC title

• H10N50/10 Primary

  Magnetoresistive devices · CPC title

• H10B61/22

  of the field-effect transistor [FET] type · CPC title