System for mutual inductance cancellation for x-type multilevel converters

Patent metadata

Field	Value
Publication number	US-2025145009-A1
Application number	US-202318501296-A
Country	US
Kind code	A1
Filing date	Nov 3, 2023
Priority date	Nov 3, 2023
Publication date	May 8, 2025
Grant date	—

Abstract

A multi-phase power inverter for an electric propulsion system includes a plurality of X-type multilevel power converters arranged between a high-voltage direct current (DC) power supply and an electric machine. Each of the plurality of X-type multilevel power converters is a solid-state integrated circuit (IC) that includes a positive DC power bus, a negative DC power bus, a neutral bus, and a plurality of semiconductor switches disposed in a stacked arrangement. The plurality of semiconductor switches is interconnected via the positive DC power bus, the negative DC power bus, and the neutral bus.

First claim

1 . A multi-phase power inverter for an electric propulsion system, the multi-phase power inverter comprising:
a plurality of X-type multilevel power converters arranged to transfer electric power between a high-voltage direct current (DC) power supply and an electric machine, wherein each of the plurality of X-type multilevel power converters is a solid-state integrated circuit (IC) including:
a positive DC power bus;
a negative DC power bus;
a first neutral bus;
a second neutral bus;
a first alternating current (AC) bus;
a second AC bus;
a plurality of semiconductor switches including a first semiconductor switch, a second semiconductor switch, a third semiconductor switch, a fourth semiconductor switch, a fifth semiconductor switch, a sixth semiconductor switch, a seventh semiconductor switch, and an eighth semiconductor switch;
a first power diode, and a second power diode;
a first heat sink adjoined to the positive DC power bus of the solid-state IC via a first direct bonded copper (DBC) substrate; and
a second heat sink adjoined to the negative DC power bus of the solid-state IC via a second DBC substrate; and
wherein the first semiconductor switch, the second semiconductor switch, the third semiconductor switch, and the fourth semiconductor switch are connected in series between the positive DC power bus and the negative DC power bus;
wherein the fifth semiconductor switch, the sixth semiconductor switch, the seventh semiconductor switch, and the eighth semiconductor switch are connected in series between the positive DC power bus and the negative DC power bus;
wherein the first semiconductor switch is connected to the second semiconductor switch at a first node, wherein the second semiconductor switch is connected to the third semiconductor switch at a second node, and wherein third semiconductor switch is connected to the fourth semiconductor switch at a third node;
wherein the fifth semiconductor switch is connected to the sixth semiconductor switch at a fourth node, wherein the sixth semiconductor switch is connected to the seventh semiconductor switch at a fifth node, and wherein the seventh semiconductor switch is connected to the eighth semiconductor switch at a sixth node;
wherein the first power diode is connected between the third node and the fourth node;
wherein the second power diode is connected between the first node and the sixth node;
wherein the second node is connected to the first AC bus; and
wherein the fifth node is connected to the second AC bus.

2 . The multi-phase power inverter as recited in claim 1 , wherein the plurality of semiconductor switches, the positive DC power bus, the negative DC power bus, the first AC bus, the second AC bus, the first power diode, and the second power diode are arranged into a plurality of tiers including:
a first tier composed of the first semiconductor switch arranged coplanar with the second semiconductor switch that is arranged coplanar with the third semiconductor switch that is arranged coplanar with the fourth semiconductor switch; a second tier composed of the first power diode, the second power diode, the positive DC power bus that is arranged coplanar with the first AC bus, and the negative DC power bus that is arranged coplanar with the negative AC bus; and a third tier composed of the second semiconductor switch arranged coplanar with the third semiconductor switch that is arranged coplanar with the sixth semiconductor switch that is arranged coplanar with the seventh semiconductor switch, wherein the first tier is arranged parallel to the second tier that is arranged parallel to the third tier.

3 . The multi-phase power inverter as recited in claim 2 , wherein the first AC bus is arranged parallel to the second AC bus.

4 . The multi-phase power inverter as recited in claim 3 , wherein the positive DC power bus is arranged parallel to the negative DC power bus.

5 . The multi-phase power inverter as recited in claim 4 , wherein the positive DC power bus and the negative DC power bus are arranged at a first end of the X-type multilevel power converter, and wherein the first AC bus and the second AC bus are arranged at a second end of the X-type multilevel power converter.

6 . The multi-phase power inverter as recited in claim 2 , wherein the first semiconductor switch, the second semiconductor switch, the third semiconductor switch, and the fourth semiconductor switch are adjoined to a first side of the first DBC substrate, and the first heat sink is adjoined to a second side of the first DBC substrate; and
wherein the fifth semiconductor switch, the sixth semiconductor switch, the seventh semiconductor switch, and the eighth semiconductor switch are adjoined to a first side of the second DBC substrate, and the second heat sink is adjoined to a second side of the second DBC substrate.

7 . The multi-phase power inverter as recited in claim 1 , wherein the plurality of semiconductor switches, the positive DC power bus, the negative DC power bus, the first AC bus, the second AC bus, the first power diode, and the second power diode are arranged into a plurality of tiers including:
a first tier composed of the first semiconductor switch arranged coplanar with the second semiconductor switch that is arranged coplanar with the third semiconductor switch that is arranged coplanar with the fourth semiconductor switch, the positive DC power bus, and the first AC bus; a second tier composed of the first power diode and the second power diode; and a third tier composed of the second semiconductor switch arranged coplanar with the third semiconductor switch that is arranged coplanar with the sixth semiconductor switch that is arranged coplanar with the seventh semiconductor switch, the negative DC power bus, and the second AC bus; and wherein the first tier is arranged parallel to the second tier that is arranged parallel to the third tier.

8 . The multi-phase power inverter as recited in claim 7 , wherein the first AC bus is arranged parallel to the second AC bus.

9 . The multi-phase power inverter as recited in claim 7 , wherein the positive DC power bus is arranged parallel to the negative DC power bus.

10 . The multi-phase power inverter as recited in claim 1 , wherein the first semiconductor switch, the second semiconductor switch, the third semiconductor switch, and the fourth semiconductor switch are adjoined to a first side of the first DBC substrate, and the first heat sink is adjoined to a second side of the first DBC substrate; and
wherein the fifth semiconductor switch, the sixth semiconductor switch, the seventh semiconductor switch, and the eighth semiconductor switch are adjoined to a first side of the second DBC substrate, and the second heat sink is adjoined to a second side of the second DBC substrate.

11 . An X-type multilevel power converter for a multi-phase electric power inverter, the X-type multilevel power converter comprising:
a solid-state integrated circuit (IC) having:
a positive direct current (DC) power bus;
a negative DC power bus;
a first neutral bus;
a second neutral bus;
a first alternating current (AC) bus;
a second AC bus;
a plurality of semiconductor switches interconnected via the positive DC power bus, the negative DC power bus, the first neutral bus, and the second neutral bus, the plurality of semiconductor switches including:
a first semiconductor switch connected at a first node;
a second semiconductor switch connected to the first semiconductor switch at the first node, the first semiconductor switch arranged in series with the second semiconductor switch between the first AC bus and the positive DC power bus, wherein the first AC bus is con

Assignees

• Gm Global Tech Operations Llc

Inventors

• Luo Yilun
• Kim Junghoon
• Alam Khorshed Mohammed
• Namuduri Chandra S
• Prasad Rashmi

Classifications

• H02M1/327

  against abnormal temperatures · CPC title

• H02M7/483

  Converters with outputs that each can have more than two voltages levels · CPC title

• H02M7/003

  Constructional details, e.g. physical layout, assembly, wiring or busbar connections · CPC title

• B60L2210/46

  with more than three phases · CPC title

• B60L15/007 Primary

  Physical arrangements or structures of drive train converters specially adapted for the propulsion motors of electric vehicles · CPC title