Asynchronous analog to digital converter

Patent metadata

Field	Value
Publication number	US-2025141462-A1
Application number	US-202318498672-A
Country	US
Kind code	A1
Filing date	Oct 31, 2023
Priority date	Oct 31, 2023
Publication date	May 1, 2025
Grant date	—

Abstract

In described examples, an integrated circuit (IC) includes multiple subcircuits. The subcircuits include a first subcircuit that receives a current and sinks a portion of the current that is responsive to a threshold. In response to the current being greater than the threshold, the first subcircuit provides a difference between the current and the portion to a second subcircuit and asserts a signal corresponding to an ordinality of the first subcircuit. The second subcircuit is configured to repeat the actions with respect to the first subcircuit, with the second subcircuit in place of the first subcircuit and a third subcircuit in place of the second subcircuit, and with the difference in place of the current, in response to the IC comprising the third subcircuit.

First claim

What is claimed is:

1 . An integrated circuit (IC) comprising:
a first current source having a terminal and configured to provide a first current at the terminal; a second current source having a terminal and configured to provide a second current at the terminal; an operational amplifier (op-amp) having a first input, a second input, and an output; multiple first transistors each having a first terminal, a second terminal, and a gate, the gates of the first transistors coupled together, and the first terminal of a first one of the first transistors coupled to the second input of the op-amp and the terminal of the first current source; a second transistor having a first terminal, a second terminal, and a gate; and multiple third transistors each having a first terminal, a second terminal, and a gate, the gates of the third transistors coupled to the first terminal and the gate of the second transistor and to the terminal of the second current source, the first terminals of the third transistors coupled to second terminals of corresponding ones of the first transistors, and the second terminals of the third transistors coupled together; wherein the first transistors are coupled in series between the terminal of the first current source and the first terminal of one of the third transistors, so that first terminals of first transistors other than the first one of the first transistors are coupled to second terminals of respective ones of the first transistors.

2 . The IC of claim 1 , wherein each of the first transistors has a bulk terminal coupled to the second input of the op-amp and the terminal of the first current source.

3 . The IC of claim 1 , further including:
multiple fourth transistors each having a first terminal, a second terminal, and a gate, gates of respective ones of the fourth transistors coupled to second terminals of corresponding ones of the first transistors and first terminals of corresponding ones of the third transistors; and multiple fifth transistors each having a first terminal, a second terminal, and a gate, the gates of the fifth transistors coupled to the gates of the third transistors, the first terminals of respective ones of the fifth transistors coupled to second terminals of corresponding ones of the fourth transistors, and the second terminals of the fifth transistors coupled to the second terminals of the third transistors.

4 . The IC of claim 3 ,
wherein the op-amp is a first op-amp; further comprising a second op-amp having a first terminal, a second terminal, and an output, the first terminal and the output of the second op-amp coupled to the first terminals of the fourth transistors.

5 . The IC of claim 1 , further including a fourth transistor having a first terminal, a second terminal, and a gate, the gate of the fourth transistor coupled to the gates of the first transistors, and the first terminal of the fourth transistor coupled to the second input of the op-amp and the terminal of the first current source.

6 . The IC of claim 1 ,
wherein the first current source includes a first resistor and the first current source is configured to generate the first current in response to a resistance of the first resistor; wherein the second current source includes a second resistor and the second current source is configured to generate the second current in response to a resistance of the second resistor; and wherein the first and second resistors are a same type of resistor.

7 . An integrated circuit (IC) comprising:
a first subcircuit configured to receive a first current, sink a portion of the first current that is responsive to a first threshold, and in response to the first current being greater than the first threshold, provide a second current that is a remainder of the first current to a second subcircuit and assert a first output signal; wherein the second subcircuit is configured to sink a portion of the second current that is responsive to a second threshold, and in response to the second current being greater than the second threshold assert a second output signal.

8 . The IC of claim 7 ,
wherein the first current is responsive to a first voltage, a second voltage, and a resistance of a first resistor; and wherein the portion of the first current is responsive to a third voltage and a resistance of a second resistor.

9 . The IC of claim 8 , wherein the first voltage is responsive to negative feedback of an operational amplifier.

10 . The IC of claim 7 , wherein the portion of the first current equals the threshold.

11 . The IC of claim 7 , wherein the first subcircuit is configured to deassert the first output signal in response to the first current being less than the threshold.

12 . The IC of claim 7 , wherein the subcircuits are configured to asynchronously perform the receive action, the sink action, and the provide action.

13 . The IC of claim 7 , further including:
a control circuit; and a voltage regulator including a switch; wherein the subcircuits are coupled to provide the signals to the control circuit; and wherein the control circuit is coupled to the voltage regulator, and the control circuit is configured to control the switch of the voltage regulator in response to the signals.

14 . A system comprising:
an analog to digital converter including:
a first current source having a terminal and configured to provide a first current at the terminal;
a second current source having a terminal and configured to provide a second current at the terminal;
an operational amplifier (op-amp) having a first input, a second input, and an output;
a first transistor having a first terminal coupled to the terminal of the first current source, a second terminal, and a gate;
a second transistor having a first terminal coupled to the second terminal of the first transistor, a second terminal, and a gate coupled to the gate of the first transistor;
a third transistor having a first terminal, a second terminal, and a gate;
a fourth transistor having a first terminal coupled to the second terminal of the first transistor, a second terminal, and a gate coupled to the first terminal and the gate of the third transistor and to the terminal of the second current source;
a fifth transistor having a first terminal coupled to the second terminal of the second transistor, a second terminal coupled to the second terminal of the fourth transistor, and a gate coupled to the first terminal and the gate of the third transistor and to the terminal of the second current source; and
an output circuit having a first control terminal coupled to the second terminal of the first transistor, a second control terminal coupled to the second terminal of the second transistor, a first output terminal, and a second output terminal;
a control circuit including a first input coupled to the first output terminal of the output circuit, a second input coupled to the second output terminal of the output circuit, and an output; a gate driver including an input and an output, the input of the gate driver coupled to the output of the control circuit; and a voltage regulator including a switch having a control terminal, the control terminal of the switch coupled to the output of the gate driver.

15 . The system of claim 14 , wherein the output circuit includes:
a sixth transistor having a first terminal, a second terminal, and a gate, the gate of the sixth transistor coupled to the first control terminal of the output circuit; and a seventh transistor having a first terminal, a second terminal, and a gate, the gate of the seventh transistor

Assignees

• Texas Instruments Inc

Inventors

• Kadlimatti Venkatesh
• Mathew Rinu

Classifications

• H03M1/462

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• G05F3/02

  Regulating voltage or current · CPC title

• H03M1/125 Primary

  Asynchronous, i.e. free-running operation within each conversion cycle · CPC title