Array Base plate, display panel and display device

Patent metadata

Field	Value
Publication number	US-2025140184-A1
Application number	US-202318683639-A
Country	US
Kind code	A1
Filing date	Jan 4, 2023
Priority date	Jan 4, 2023
Publication date	May 1, 2025
Grant date	—

Abstract

An array base plate includes a substrate; a plurality of sub-pixels; and a plurality of gate lines and a plurality of data lines, wherein the plurality of gate lines intersect with the plurality of data lines, each of the sub-pixels is located at a position limited by two adjacent gate lines and two adjacent data lines, and each of the sub-pixels includes a pixel driving circuit and a light emitting device that are connected; wherein the pixel driving circuit includes: a drive module and a first control module, the pixel driving circuit further includes an auxiliary anode, the auxiliary anode is located between the anode and the substrate, and the auxiliary anode is electrically connected to the anode; the first power signal line includes a first part and a second part that are electrically connected.

First claim

1 . An array base plate, comprising:
a substrate; a plurality of sub-pixels that are located on the substrate and arranged in array; and a plurality of gate lines and a plurality of data lines, wherein the plurality of gate lines intersect with the plurality of data lines, each of the sub-pixels is located at a position limited by two adjacent gate lines and two adjacent data lines, and each of the sub-pixels comprises a pixel driving circuit and a light emitting device that are electrically connected; wherein the pixel driving circuit comprises: a drive module electrically connected to a first node, a second node and an anode of the light emitting device, wherein the drive module is configured for conducting a path between the second node and the anode under control of a voltage of the first node, and generating a current in the path to make the light emitting device emit light; the second node is coupled to the first power signal line; and a first control module electrically connected to a first control signal line, a second power signal line and the anode of the light emitting device, wherein the first control module is configured for transferring a second power signal transmitted by the second power signal line to the anode under control of a first control signal transmitted by the first control signal line; wherein the pixel driving circuit further comprises an auxiliary anode, the auxiliary anode is located between the anode and the substrate, and the auxiliary anode is electrically connected to the anode; the first power signal line comprises a first part and a second part that are electrically connected, the first part of the first power signal line and the first control signal line are arranged on a same layer, and the second part of the first power signal line and the auxiliary anode are arranged on a same layer.

2 . The array base plate according to claim 1 , wherein the pixel driving circuit further comprises a second control module;
the second control module is electrically connected to the first power signal line, a second control signal line and the drive module, and configured for transferring a first power signal transmitted by the first power signal line to the drive module under control of a second control signal transmitted by the second control signal line, and assisting in generating the current in the path to make the light emitting device emit light; wherein an orthographic projection of the second control module on the substrate overlaps with an orthographic projection of the second part of the first power signal line on the substrate.

3 . The array base plate according to claim 2 , wherein the pixel driving circuit further comprises an input module;
the input module is electrically connected to the gate lines, the data lines and the first node, and configured for writing data signals transmitted by the data lines into the first node under control of scan signals transmitted by the gate lines; wherein an orthographic projection of the input module on the substrate overlaps with orthographic projections of the gate lines on the substrate, and the orthographic projection of the input module on the substrate overlaps with an orthographic projection of the second control signal line on the substrate.

4 . The array base plate according to claim 3 , wherein the input module and the second control module are located at a same side of the drive module, and the first control module is located at a side of the drive module away from the second control module.

5 . The array base plate according to claim 4 , wherein the input module comprises a first transistor, the drive module comprises a driving transistor, the second control module comprises a second transistor, and the first control module comprises a third transistor;
a gate of the first transistor is electrically connected to the gate line, a source of the first transistor is electrically connected to the data line, and a drain of the first transistor is electrically connected to a gate of the driving transistor; a gate of the second transistor is electrically connected to the second control signal line, a source of the second transistor is electrically connected to the first power signal line, and a drain of the second transistor is electrically connected to a source of the driving transistor; and a gate of the third transistor is electrically connected to the first control signal line, a source of the third transistor is electrically connected to a drain of the driving transistor, and a drain of the third transistor is electrically connected to the second power signal line.

6 . The array base plate according to claim 5 , wherein the pixel driving circuit further comprises a first wiring, an extension direction of the first wiring intersects with an extension direction of the first control signal line, the first wiring is electrically connected to the gate of the third transistor and the first control signal line, and the first wiring and the data lines are arranged on a same layer.

7 . The array base plate according to claim 6 , wherein an orthographic projection of the gate of the third transistor on the substrate partially overlaps with an orthographic projection of the first control signal line on the substrate, an orthographic projection of the first wiring on the substrate partially overlaps with the orthographic projection of the gate of the third transistor on the substrate, the orthographic projection of the first wiring on the substrate extends from a side of the gate of the third transistor close to the first control signal line to a side of the gate of the third transistor away from the first control signal line, and the orthographic projection of the first wiring on the substrate overlaps with an orthographic projection of an active region of the third transistor on the substrate.

8 . The array base plate according to claim 6 , wherein the pixel driving circuit further comprises a second wiring, an extension direction of the second wiring is consistent with an extension direction of the data lines, the second wiring is electrically connected to the source of the second transistor and the first power signal line, and the second wiring and the data lines are arranged on the same layer.

9 . The array base plate according to claim 8 , wherein the extension direction of the second wiring intersects with an extension direction of the gate lines, and an orthographic projection of the second wiring on the substrate partially overlaps with the orthographic projection of the gate lines on the substrate; and
the orthographic projection of the second wiring on the substrate extends from a position where an orthographic projection of the source of the second transistor on the substrate is located to a position where an orthographic projection of the first part of the first power signal line on the substrate is located.

10 . The array base plate according to claim 8 , wherein the orthographic projection of the second control signal line on the substrate overlaps with orthographic projections of the gate of the first transistor and the gate of the second transistor on the substrate; and
the orthographic projection of the gate lines on the substrate overlaps with the orthographic projection of the gate of the first transistor on the substrate, and the orthographic projection of the gate lines on the substrate overlaps with an orthographic projection of an active region of the first transistor on the substrate.

11 . The array base plate according to claim 10 , wherein in a region where the same second control signal line is located, a distance from the gate of the first transistor along a direction parallel to the data l

Assignees

• Yunnan Invensight Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Fan Longfei
• Ma Yaoxi
• Chen Xiaochuan
• Shan Qingshan
• Lu Pengcheng
• Yang Shengji
• Jiang Shanghong

Classifications

• G09G3/32 Primary

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2320/0209

  Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title