Self-aligned gate endcap (sage) architectures with improved cap

Patent metadata

Field	Value
Publication number	US-2025133811-A1
Application number	US-202419000050-A
Country	US
Kind code	A1
Filing date	Dec 23, 2024
Priority date	Dec 21, 2021
Publication date	Apr 24, 2025
Grant date	—

Abstract

Self-aligned gate endcap (SAGE) architectures with improved caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with improved caps, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first gate structure and the second gate structure. The gate endcap isolation structure has a higher-k dielectric cap layer on a lower-k dielectric wall. The higher-k dielectric cap layer includes hafnium and oxygen and has 70% or greater monoclinic crystallinity.

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
a first pair of fins on a substrate; a second pair of fins on the substrate, the second pair of fins laterally spaced apart from the first pair of fins; a first gate stack over an upper portion of the first pair of fins; a second gate stack over an upper portion of the second pair of fins; a first gate endcap wall laterally between the first pair of fins and the second pair of fins, the first gate endcap wall in contact with the first gate stack and the second gate stack, and the first gate endcap wall having an uppermost surface at a same level as an uppermost surface of the first gate stack and the second gate stack; a second gate endcap wall laterally spaced apart from a side of the second pair of fins opposite the first gate endcap wall, and the second gate endcap wall in contact with the second gate stack; and a trench isolation structure laterally adjacent to a lower portion of the first pair of fins, a lower portion of the second pair of fins, a lower portion of the first gate endcap wall, and a lower portion of the second gate endcap wall, the trench isolation structure having a bottommost surface below a bottommost surface of the first gate endcap wall and below a bottommost surface of the second gate endcap wall.

2 . The integrated circuit structure of claim 1 , wherein the first gate stack comprises a first high-k dielectric layer in contact with a first sidewall of the first gate endcap wall, and wherein the second gate stack comprises a second high-k dielectric layer in contact with a second sidewall of the second gate endcap wall, the second sidewall laterally opposite to the first sidewall.

3 . The integrated circuit structure of claim 2 , wherein first high-k dielectric layer is along the first sidewall of the first gate endcap wall, and wherein the second high-k dielectric layer is along the second sidewall of the second gate endcap wall.

4 . The integrated circuit structure of claim 1 , wherein the first gate stack has a same composition as the second gate stack.

5 . The integrated circuit structure of claim 1 , further comprising:
a dielectric cap layer on the second gate endcap wall.

6 . The integrated circuit structure of claim 1 , further comprising:
a third gate endcap wall laterally spaced apart from a side of the first pair of fins opposite the first gate endcap wall.

7 . The integrated circuit structure of claim 1 , further comprising:
a local conductive interconnect over the first gate endcap wall.

8 . An integrated circuit structure, comprising:
a first fin and a second fin on a substrate, the second fin laterally spaced apart from the first fin; a third fin and a fourth fin on the substrate, the third fin laterally spaced apart from the second fin, and the fourth fin laterally spaced apart from the third fin; a first gate stack over an upper portion of the first fin and an upper portion of the second fin; a second gate stack over an upper portion of the third fin and an upper portion of the fourth fin; a first gate endcap wall laterally between the second fin and the third fin, the first gate endcap wall in contact with the first gate stack and the second gate stack, and the first gate endcap wall having an uppermost surface at a same level as an uppermost surface of the first gate stack and the second gate stack; a second gate endcap wall laterally spaced apart from a side of the fourth fin opposite the first gate endcap wall, and the second gate endcap wall in contact with the second gate stack; a first trench isolation region between a lower portion of the second fin and a lower portion of the first gate endcap wall; a second trench isolation region between the first gate endcap wall and a lower portion of the third fin, wherein a bottommost surface of the first gate endcap wall extends no further than a bottommost surface of the first trench isolation region and a bottommost surface of the second trench isolation region; and a third trench isolation region between a lower portion of the fourth fin and a lower portion of the second gate endcap wall, wherein a bottommost surface of the second gate endcap wall extends no further than a bottommost surface of the third trench isolation region.

9 . The integrated circuit structure of claim 8 , wherein the first gate stack comprises a first high-k dielectric layer in contact with a first sidewall of the first gate endcap wall, and wherein the second gate stack comprises a second high-k dielectric layer in contact with a second sidewall of the second gate endcap wall, the second sidewall laterally opposite to the first sidewall.

10 . The integrated circuit structure of claim 9 , wherein first high-k dielectric layer is along the first sidewall of the first gate endcap wall, and wherein the second high-k dielectric layer is along the second sidewall of the second gate endcap wall.

11 . The integrated circuit structure of claim 8 , wherein the first gate stack has a same composition as the second gate stack.

12 . The integrated circuit structure of claim 8 , further comprising:
a dielectric cap layer on the second gate endcap wall.

13 . The integrated circuit structure of claim 8 , further comprising:
a local conductive interconnect over the first gate endcap wall.

14 . An integrated circuit structure, comprising:
a first pair of nanowires above a substrate; a second pair of nanowires on the substrate, the second pair of nanowires laterally spaced apart from the first pair of nanowires; a first gate stack over an upper portion of the first pair of nanowires; a second gate stack over an upper portion of the second pair of nanowires; a first gate endcap wall laterally between the first pair of nanowires and the second pair of nanowires, the first gate endcap wall in contact with the first gate stack and the second gate stack, and the first gate endcap wall having an uppermost surface at a same level as an uppermost surface of the first gate stack and the second gate stack; a second gate endcap wall laterally spaced apart from a side of the second pair of nanowires opposite the first gate endcap wall, and the second gate endcap wall in contact with the second gate stack; and a trench isolation structure laterally adjacent to a lower portion of the first gate endcap wall, and a lower portion of the second gate endcap wall, the trench isolation structure having a bottommost surface below a bottommost surface of the first gate endcap wall and below a bottommost surface of the second gate endcap wall.

15 . The integrated circuit structure of claim 14 , wherein the first gate stack comprises a first high-k dielectric layer in contact with a first sidewall of the first gate endcap wall, and wherein the second gate stack comprises a second high-k dielectric layer in contact with a second sidewall of the second gate endcap wall, the second sidewall laterally opposite to the first sidewall.

16 . The integrated circuit structure of claim 15 , wherein first high-k dielectric layer is along the first sidewall of the first gate endcap wall, and wherein the second high-k dielectric layer is along the second sidewall of the second gate endcap wall.

17 . The integrated circuit structure of claim 14 , wherein the first gate stack has a same composition as the second gate stack.

18 . The integrated circuit structure of claim 14 , further comprising:
a dielectric cap layer on the second gate endcap wall.

19 . The integrated circuit structure of

Assignees

• Intel Corp

Inventors

• Radlinger Christine
• Wacharasindhu Tongtawee
• Baran Andre
• Chikkadi Kiran
• Merrill Devin
• Dendge Nilesh
• Towner David J
• Kenyon Christopher

Classifications

• H10D84/834 Primary

  comprising FinFETs · CPC title

• H10D64/514

  characterised by the insulating layers · CPC title

• H10D30/0245

  by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/0158

  the components including FinFETs · CPC title