Method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-2025132198-A1
Application number	US-202418669981-A
Country	US
Kind code	A1
Filing date	May 21, 2024
Priority date	Oct 20, 2023
Publication date	Apr 24, 2025
Grant date	—

Abstract

A method of manufacturing a semiconductor device, the method includes forming interconnection lines buried in a first interlayer insulating layer, the interconnection lines having exposed upper surfaces, selectively forming a preliminary low dielectric constant layer including a polymer containing silicon (Si) or an oligomer containing silicon (Si) on an upper surface of the first interlayer insulating layer, forming a low dielectric constant layer by performing ultraviolet (UV) and ozone (O 3 ) treatments on the preliminary low dielectric constant layer, forming an etch stop layer on the low dielectric constant layer, forming a second interlayer insulating layer on the etch stop layer, and forming a via connected to at least one of the interconnection lines by removing a portion of the second interlayer insulating layer and depositing a conductive material. The via has a shape bent along an upper surface and a side surface of the low dielectric constant layer.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, the method comprising:
forming interconnection lines buried in a first interlayer insulating layer, the interconnection lines having exposed upper surfaces; selectively forming a preliminary low dielectric constant layer including a polymer containing silicon (Si) or an oligomer containing silicon (Si) on an upper surface of the first interlayer insulating layer; forming a low dielectric constant layer by performing ultraviolet (UV) and ozone (O 3 ) treatments on the preliminary low dielectric constant layer; forming an etch stop layer on the low dielectric constant layer; forming a second interlayer insulating layer on the etch stop layer; and forming a via connected to at least one of the interconnection lines by removing a portion of the second interlayer insulating layer and depositing a conductive material, wherein the via has a shape bent along an upper surface and a side surface of the low dielectric constant layer.

2 . The method of claim 1 , wherein the low dielectric constant layer includes SiO w C x F y H z (0<w, 0≤x, 0≤y, 0≤z).

3 . The method of claim 1 , wherein the low dielectric constant layer includes carbon (C).

4 . The method of claim 1 , further comprising:
forming a mask layer including a polymer not containing silicon (Si) or an oligomer not containing silicon (Si) on the upper surfaces of the interconnection lines, before the preliminary low dielectric constant layer is formed.

5 . The method of claim 4 , wherein the mask layer is removed during the ultraviolet (UV) and ozone (O 3 ) treatments.

6 . The method of claim 1 , wherein a thickness of the low dielectric constant layer is in a range of about 1 nm to about 50 nm.

7 . The method of claim 1 , wherein the polymer containing silicon (Si) or the oligomer containing silicon (Si) includes hydroxyl-terminated polydimethylsiloxane (PDMS-OH).

8 . The method of claim 1 , wherein the etch stop layer is formed to expose the upper surfaces of the interconnection lines.

9 . The method of claim 8 , wherein the etch stop layer further exposes side surfaces of the low dielectric constant layer.

10 . The method of claim 1 , further comprising:
cleaning the upper surfaces of the interconnection lines in a reducing atmosphere, before the etch stop layer is formed.

11 . The method of claim 10 , wherein an oxide layer, formed on the upper surfaces of the interconnection lines, is removed by the cleaning.

12 . The method of claim 1 , wherein levels of the upper surfaces of the interconnection lines are a same level.

13 . A method of manufacturing a semiconductor device, the method comprising:
preparing a substrate structure including a first interlayer insulating layer and interconnection lines buried in the first interlayer insulating layer, the interconnection lines having exposed upper surfaces; selectively forming a preliminary low dielectric constant layer including a polymer containing silicon (Si) or an oligomer containing silicon (Si) on an upper surface of the first interlayer insulating layer; forming a low dielectric constant layer by oxidizing the preliminary low dielectric constant layer; forming a second interlayer insulating layer on the low dielectric constant layer; and forming a via partially passing through the second interlayer insulating layer, the via connected to at least one of the interconnection lines, wherein the via is in contact with a portion of an upper surface of the low dielectric constant layer, and the low dielectric constant layer includes SiO w C x F y H z (0<w, 0≤x, 0≤y, 0≤z).

14 . The method of claim 13 , wherein the low dielectric constant layer includes SiO w C x F y H z (0<w, 0<x, 0≤y, 0≤z).

15 . The method of claim 13 , wherein in the forming the low dielectric constant layer, the preliminary low dielectric constant layer is oxidized using at least one of ultraviolet (UV) and ozone (O 3 ) treatments, corona discharge, oxygen plasma, or oxygen radicals.

16 . The method of claim 13 , wherein the via has a bent shape along the upper surface and a side surface of the low dielectric constant layer.

17 . The method of claim 13 , further comprising:
forming an etch stop layer on the low dielectric constant layer before the second interlayer insulating layer is formed, wherein the etch stop layer includes metal oxide.

18 . A method of manufacturing a semiconductor device, the method comprising:
preparing a substrate structure including a first interlayer insulating layer and first and second interconnection lines buried in the first interlayer insulating layer, the first and second interconnection lines having exposed upper surfaces, the first and second interconnection lines spaced apart from each other in a horizontal direction; selectively forming a preliminary low dielectric constant layer including a polymer containing silicon (Si) or an oligomer containing silicon (Si) on an upper surface of the first interlayer insulating layer; forming a low dielectric constant layer by performing ultraviolet (UV) and ozone (O 3 ) treatments on the preliminary low dielectric constant layer; forming a second interlayer insulating layer on the low dielectric constant layer; and forming a via partially passing through the second interlayer insulating layer, the via connected to the second interconnection line, wherein a region of the via closest to the first interconnection line is positioned on a level higher than the upper surface of the first interconnection line.

19 . The method of claim 18 , wherein a dielectric constant of the low dielectric constant layer is controlled by ultraviolet (UV) and ozone (O 3 ) treatment time and/or a ratio of ultraviolet (UV) irradiation time and ozone (O 3 ) treatment time.

20 . The method of claim 18 , wherein a thickness of the low dielectric constant layer is controlled by adjusting a molecular weight of the polymer containing silicon (Si) or the oligomer containing silicon (Si).

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Yunho
• Kim Minsik
• Kim Yeonuk
• Oh Seran
• Lee Byounghoon
• Lee Jangeun

Classifications

• H10P95/08

  Planarisation of organic insulating materials · CPC title

• H10W20/095 Primary

  by irradiating with electromagnetic or particle radiation (plasma treatment H10W20/096) · CPC title

• H10W20/089 Primary

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title