Advanced wavelet filtering for accelerated deep learning

Patent metadata

Field	Value
Publication number	US-2025131237-A1
Application number	US-202419001087-A
Country	US
Kind code	A1
Filing date	Dec 24, 2024
Priority date	Oct 16, 2019
Publication date	Apr 24, 2025
Grant date	—

Abstract

Techniques in wavelet filtering for advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements comprising a portion of a neural network accelerator performs flow-based computations on wavelets of data. Each processing element comprises a compute element to execute programmed instructions using the data and a router to route the wavelets in accordance with virtual channel specifiers. Each processing element is enabled to perform local filtering of wavelets received at the processing element, selectively, conditionally, and/or optionally discarding zero or more of the received wavelets, thereby preventing further processing of the discarded wavelets. The wavelet filtering is performed by one or more configurable wavelet filters operable in various modes, such as counter, sparse, and range modes.

First claim

1 .- 64 . (canceled)

65 . A method comprising:
receiving, at a wavelet filter of a processing element, a wavelet associated with a first virtual channel specifier; and based on determining:
that the first virtual channel specifier is different from a second virtual channel specifier associated with the wavelet filter, assigning the wavelet to one or more input queues of the processing element associated with the first virtual channel specifier, and
that the first virtual channel specifier is associated with the wavelet filter, preventing the wavelet from being processed by the processing element.

66 . The method of claim 65 , further comprising, based on the determining that the first virtual channel specifier is associated with the wavelet filter, preventing transmission of the wavelet.

67 . The method of claim 65 , further comprising determining whether the wavelet is one of a control wavelet type or a data wavelet type.

68 . The method of claim 65 , wherein the wavelet filter comprises a counter, the method further comprising updating the counter based on the first virtual channel specifier.

69 . The method of claim 68 , wherein the wavelet filter comprises one or more configuration registers indicating a virtual channel specifier associated with the wavelet filter.

70 . The method of claim 69 , wherein the one or more configuration registers comprise one or more fields indicating a filter operating mode, and wherein the updating the counter is based in part on the filter operating mode.

71 . The method of claim 70 , wherein the filter operating mode is one of a counter filter mode, a sparse filter mode, or a range filter mode.

72 . The method of claim 71 , wherein the filter operating mode is the counter filter mode, and wherein the one or more configuration registers indicate a maximum pass value of the wavelet filter, the method further comprising:
comparing a value of the counter and the maximum pass value; and wherein the assigning the wavelet to the one or more input queues is based in part on the comparing.

73 . The method of claim 71 , wherein the filter operating mode is the sparse filter mode, and wherein the one or more configuration registers indicate a counter threshold of the wavelet filter, the method further comprising:
comparing the counter to the counter threshold; and wherein the assigning the wavelet to the one or more input queues is based in part on the comparing.

74 . The method of claim 65 , wherein the first virtual channel specifier indicates a first virtual channel of a plurality of virtual channels of the processing element.

75 . A system comprising:
a wavelet filter of a processing element, the wavelet filter configured to receive a wavelet associated with a first virtual channel specifier; and processing circuitry configured to, based on determining:
that the first virtual channel specifier is different from a second virtual channel specifier associated with the wavelet filter, assign the wavelet to one or more input queues of the processing element associated with the first virtual channel specifier, and
that the first virtual channel specifier is associated with the wavelet filter, prevent the wavelet from being processed by the processing element.

76 . The system of claim 75 , wherein the processing circuitry is further configured to:
based on determining that the first virtual channel specifier is associated with the wavelet filter, prevent transmission of the wavelet.

77 . The system of claim 75 , wherein the processing circuitry is further configured to:
determine whether the wavelet is one of a control wavelet type or a data wavelet type.

78 . The system of claim 75 , wherein the wavelet filter comprises a counter, and wherein the processing circuitry is further configured to update the counter based on the first virtual channel specifier.

79 . The system of claim 78 , wherein the wavelet filter comprises one or more configuration registers indicating a virtual channel specifier associated with the wavelet filter.

80 . The system of claim 79 , wherein the one or more configuration registers comprise one or more fields indicating a filter operating mode, and wherein the processing circuitry is configured to update the counter based in part on the filter operating mode.

81 . The system of claim 80 , wherein the filter operating mode is one of a counter filter mode, a sparse filter mode, or a range filter mode.

82 . The system of claim 81 , wherein the filter operating mode is the counter filter mode, wherein the one or more configuration registers indicate a maximum pass value of the wavelet filter, and wherein the processing circuitry is further configured to:
compare a value of the counter and the maximum pass value; and assign the wavelet to the one or more input queues based in part on the comparison.

83 . The system of claim 81 , wherein the filter operating mode is the sparse filter mode, wherein the one or more configuration registers indicate a counter threshold of the wavelet filter, and wherein the processing circuitry is further configured to:
compare the counter to the counter threshold; and assign the wavelet to the one or more input queues based in part on the comparison.

84 . The system of claim 75 , wherein the first virtual channel specifier indicates a first virtual channel of a plurality of virtual channels of the processing element.

Assignees

• Cerebras Systems Inc

Inventors

• Morrison Michael
• James Michael Edwin
• Lie Sean
• Arekapudi Srikanth
• Lauterbach Gary R

Classifications

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06N3/0495

  Quantised networks; Sparse networks; Compressed networks · CPC title

• G06N3/09

  Supervised learning · CPC title

• G06F9/3888

  controlled by a single instruction for multiple threads [SIMT] in parallel · CPC title

• G06F13/42

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title