Storing memory array operational information in non-volatile subarrays

Patent metadata

Field	Value
Publication number	US-2025130908-A1
Application number	US-202418937428-A
Country	US
Kind code	A1
Filing date	Nov 5, 2024
Priority date	Sep 16, 2016
Publication date	Apr 24, 2025
Grant date	—

Abstract

Methods, systems, and apparatuses for storing operational information related to operation of a non-volatile array are described. For example, the operational information may be stored in a in a subarray of a memory array for use in analyzing errors in the operation of memory array. In some examples, an array driver may be located between a command decoder and a memory array. The array driver may receive a signal pattern used to execute an access instruction for accessing non-volatile memory cells of a memory array and may access the first set of non-volatile memory cells according to the signal pattern. The array driver may also store the access instruction (e.g., the binary representation of the access instruction) at a non-volatile subarray of the memory array.

First claim

1 . (canceled)

2 . A memory system, comprising:
one or more processors associated with one or more memory devices and configured to cause the memory system to:
receive an access instruction for accessing a first set of memory cells of a memory array;
access the first set of memory cells based on applying the access instruction to the memory array; and
store the access instruction at a second set of memory cells in the memory array, the second set of memory cells comprising a subarray of the first set of memory cells of the memory array.

3 . The memory system of claim 2 , wherein the one or more processors are further configured to cause the memory system to:
determine a binary representation of the access instruction based at least in part on a plurality of received signals, wherein, to store the access instruction, the one or more processors are further configured to:
store the binary representation of the access instruction at the second set of memory cells.

4 . The memory system of claim 3 , wherein the first set of memory cells are accessed using circuitry and access patterns associated with the first set of memory cells, and wherein, to store the access instruction, the one or more processors are configured to cause the memory system to:
write the binary representation of the access instruction to the second set of memory cells using the circuitry and the access patterns associated with the first set of memory cells.

5 . The memory system of claim 4 , wherein the one or more processors are further configured to cause the memory system to:
increment a counter after storing the access instruction, wherein a value of the counter indicates which memory cells of the second set of memory cells were last written.

6 . The memory system of claim 2 , wherein the one or more processors are further configured to cause the memory system to:
relay a first plurality of signals corresponding to the access instruction or an amplified version of the first plurality of signals to corresponding input pins of the memory array.

7 . The memory system of claim 2 , wherein the one or more processors are further configured to cause the memory system to:
send a plurality of signals to a command decoder, wherein the plurality of signals corresponds to the access instruction for accessing the first set of memory cells of the memory array; receive from the command decoder a second plurality of signals corresponding to the access instruction for accessing the first set of memory cells of the memory array; and access a third set of memory cells according to the second plurality of signals.

8 . The memory system of claim 7 , wherein the one or more processors are further configured to cause the memory system to:
compare a result of accessing the third set of memory cells with an expected result; and determine a failure state of the third set of memory cells.

9 . The memory system of claim 7 , wherein the second set of memory cells is implemented as a circular buffer.

10 . The memory system of claim 2 , wherein the one or more processors are further configured to cause the memory system to:
receive an indication to begin storing the access instruction at the second set of memory cells before storing the access instruction.

11 . The memory system of claim 10 , wherein the indication comprises at least one of:
a first flag receive from an application that has experienced an operating failure, a second flag received from an error correction code component that has determined that a predetermined number of error correcting code (ECC) errors has occurred, or a trigger to enter a test mode, or any combination thereof.

12 . The memory system of claim 2 , wherein the one or more processors are further configured to cause the memory system to:
store an address of the first set of memory cells, store a value that indicates a temperature of the memory array, store a value that indicates a number of access operations performed on the memory array, store a value that indicates a voltage of the memory array, store data written to the first set of memory cells, store a value that indicates a duration between access operations, or any combination thereof.

13 . The memory system of claim 2 , wherein the one or more processors are further configured to cause the memory system to:
determine a number of memory cells in the second set of memory cells based at least in part on an amount of information to be stored at the second set of memory cells.

14 . A method at a memory system, comprising:
receiving an access instruction for accessing a first set of memory cells of a memory array of the memory system; accessing the first set of memory cells based on applying the access instruction to the memory array; and storing the access instruction at a second set of memory cells in the memory array, the second set of memory cells comprising a subarray of the first set of memory cells of the memory array.

15 . The method of claim 14 , further comprising:
determining a binary representation of the access instruction based at least in part on a plurality of received signals, wherein storing the access instruction comprises:
storing the binary representation of the access instruction at the second set of memory cells.

16 . The method of claim 15 , wherein the first set of memory cells are accessed using circuitry and access patterns associated with the first set of memory cells, and wherein storing the access instruction comprises:
writing the binary representation of the access instruction to the second set of memory cells using the circuitry and the access patterns associated with the first set of memory cells.

17 . The method of claim 16 , further comprising:
incrementing a counter after storing the access instruction, wherein a value of the counter indicates which memory cells of the second set of memory cells were last written.

18 . The method of claim 14 , further comprising:
relaying a first plurality of signals corresponding to the access instruction or an amplified version of the first plurality of signals to corresponding input pins of the memory array.

19 . The method of claim 14 , further comprising:
sending a plurality of signals to a command decoder, wherein the plurality of signals corresponds to the access instruction for accessing the first set of memory cells of the memory array; receiving from the command decoder a second plurality of signals corresponding to the access instruction for accessing the first set of memory cells of the memory array; and accessing a third set of memory cells according to the second plurality of signals.

20 . The method of claim 19 , further comprising:
comparing a result of accessing the third set of memory cells with an expected result; and determining a failure state of the third set of memory cells.

21 . A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors of a memory system to cause the memory system to:
receive an access instruction for accessing a first set of memory cells of a memory array of the memory system; access the first set of memory cells based on applying the access instruction to the memory array; and store the access instruction at a second set of memory cells in the memory array, the second set of memory cells comprising a subarray of the first set of memory cells of the memory array.

Assignees

• Micron Technology Inc

Inventors

• Kawamura Christopher John
• Derner Scott James
• Ingalls Charles L

Classifications

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title

• G11C11/2273

  Reading or sensing circuits or methods · CPC title

• G11C11/2257

  Word-line or row circuits · CPC title

• G11C11/2255

  Bit-line or column circuits · CPC title