Data processing method and data processing apparatus

US2025125906A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2025125906-A1
Application numberUS-202418999679-A
CountryUS
Kind codeA1
Filing dateDec 23, 2024
Priority dateJun 24, 2022
Publication dateApr 17, 2025
Grant date

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  5. First independent claim

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Abstract

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A data processing method comprises: separately performing inner-code encoding on n first data streams to obtain n second data streams, where the n second data streams include n inner-code codewords from the n second data streams, the n inner-code codewords include n/m codeword sets, each of the codeword sets includes m inner-code codewords, and each of the inner-code codewords includes N bits; separately performing bit interleaving on the n/m codeword sets to obtain n/m target bit sets; and separately mapping m×N bits in each of the target bit sets to obtain m×N/L modulation symbols, to obtain n×N/L modulation symbols, where every L bits are mapped to one modulation symbol, and the L bits in the modulation symbol are from L inner-code codewords, wherein the L bits in the modulation symbol are from information bits in the inner-code codewords.

First claim

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1 . A method of data processing, comprising: separately performing interleaving and encoding processing on every n 1 first data streams in no first data streams to obtain one second data stream, to obtain n 2 second data streams, wherein n 2 =n 0 /n 1 , n 0 is an integer greater than 1, and n 1 is an integer greater than 0; and separately mapping every two bits in the n 2 second data streams to one four-level pulse amplitude modulation (PAM4) symbol, to obtain n 2 PAM4 symbol data streams; wherein separately performing the interleaving and encoding processing comprises: obtaining a 0 first bit sets from each of the n 1 first data streams to obtain m=n 1 ×a 0 first bit sets, wherein outer-code encoding is respectively performed on of the n 1 first data streams or performed on the n 1 first data streams collectively, each of the first bit sets comprises K bits, and a 0 and K are integers greater than 1; separately performing a circular shift on the m first bit sets to obtain m second bit sets, wherein each of the second bit sets comprises K bits; separately performing inner-code encoding on the m second bit sets to obtain m inner-code codewords, wherein the inner-code encoding and the outer-code encoding are forward error correction (FEC) encoding, each of the m inner-code codewords comprises a second bit set and a parity bit set having N bits, N=K+P, each parity bit set comprises P bits, and P is an integer greater than or equal to 1; and obtaining, through round robin, two bits from each inner-code codeword of the m inner-code codewords to obtain a third bit set, wherein the third bit set comprises m×N bits; wherein each second data stream of the n 2 second data streams comprises a plurality of third bit sets, m×N/2 PAM4 symbols are obtained through the mapping of each of the third bit sets. 2 . The method according to claim 1 , wherein at least 10 PAM4 symbols are obtained through the performance of the interleaving and encoding processing and mapping of 20 consecutive bits in a first data stream of the n 1 first data streams, the 20 consecutive bits are from two outer-code symbols in one outer-code codeword, and any two of the at least 10 PAM4 symbols are separated by at least two PAM4 symbols in a PAM4 symbol data stream of the n 2 PAM4 symbol data streams. 3 . The method according to claim 1 , wherein quantities of bits by which the circular shift is performed on any two of the m first bit sets are different. 4 . The method according to claim 1 , wherein the m first bit sets and the m second bit sets are represented as bit matrixes, and each bit matrix of the bit matrixes comprises m rows and K columns of bits. 5 . The method according to claim 4 , wherein a second bit set of the m second bit sets is obtained by performing a right circular shift on a first bit set of the m first bit sets by δ i bits, the right circular shift satisfies a second condition that comprises: M 2 [ i ] [ j ] = M 1 [ i ] [ ( j + δ i ) ⁢ % ⁢ K ] ; . wherein M 1 [i][j] represents a bit in an i th row and a j th column in a bit matrix corresponding to the m first bit sets on which the right circular shift has not been performed, M 2 [i][j] represents a bit in an i th row and a j th column in a bit matrix corresponding to the m second bit sets obtained through the right circular shift, Y % Z represents a remainder obtained by dividing the integer Y by the integer Z, 0≤i<m, 0≤j<K, and 0≤δ i <K. 6 . The method according to claim 4 , wherein the m inner-code codewords are represented as a bit matrix comprising m rows and N columns, the m inner-code codewords and the third bit set satisfy a third condition that comprises: A [ ⌊ j / 2 ⌋ × ( m × 2 ) + ( i × 2 ) + ( j ⁢ % ⁢ 2 ) ] = M c [ i ] [ j ] . wherein M c [i][j] represents a bit in an i th row and a j th column in a bit matrix corresponding to the m inner-code codewords, A[[j/2]×(m×2)+(i×2)+(j %2)] represents a ([j/2]×(m×2)+(i×2)+(j % 2 )) th bit in the third bit set, 0≤i<m, 0≤j<N, and └⋅┘ represents a rounding-down operation. 7 . The method according to claim 4 , wherein K=120, m=8, an i th second bit set is obtained by performing a right circular shift on an i th first bit set by δ i bits, 0≤i<8, a value of δ i satisfies any one of second value items {δ 0 , δ 1 , δ 2 , δ 3 , δ 4 , δ 5 , δ 6 , δ 7 }, and the second value items {δ 0 , δ 1 , δ 2 , δ 3 , δ 4 , δ 5 , δ 6 , δ 7 } comprise: {0, 30, 60, 90, 10, 40, 70, 100}; {0, 30, 90, 60, 10, 40, 100, 70}; {0, 60, 30, 90, 10, 40, 70, 100}; {0, 60, 90, 30, 10, 70, 100, 40}; {0, 90, 30, 60, 10, 100, 40, 70}; or {0, 90, 60, 30, 10, 100, 70, 40}. 8 . The method according to claim 1 , wherein obtaining the a 0 first bit sets from each of the n 1 first data streams comprises: performing convolutional interleaving processing on

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Classifications

  • using multilevel codes · CPC title

  • Use of interleaving (interleaving per se H03M13/27) · CPC title

  • Convolutional interleaver; Interleavers using shift-registers or delay lines like, e.g. Ramsey type interleaver · CPC title

  • Distributed coding, e.g. network coding, involving channel coding (coding in both space and time H04L1/0618; cooperative diversity H04B7/022) · CPC title

  • Channel splitting in point-to-point links · CPC title

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What does patent US2025125906A1 cover?
A data processing method comprises: separately performing inner-code encoding on n first data streams to obtain n second data streams, where the n second data streams include n inner-code codewords from the n second data streams, the n inner-code codewords include n/m codeword sets, each of the codeword sets includes m inner-code codewords, and each of the inner-code codewords includes N bits; …
Who is the assignee on this patent?
Huawei Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification H03M13/2732. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Apr 17 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).