Semiconductor circuit device

Patent metadata

Field	Value
Publication number	US-2025125308-A1
Application number	US-202418984238-A
Country	US
Kind code	A1
Filing date	Dec 17, 2024
Priority date	Feb 14, 2020
Publication date	Apr 17, 2025
Grant date	—

Abstract

A layout of electrode pads on a front surface of a first semiconductor chip is different from a layout of them on a second semiconductor chip. An overall layout of the semiconductor chips mounted on the insulated substrate and the layouts of the electrode pads on the front surfaces of the semiconductor chips including the first and second semiconductor chips are determined so that a value of a resistance component and/or a value of a reactance component between each two electrode pads that are the same type respectively on different semiconductor chips and are connected in parallel become the same. As a result, current waveform oscillation between semiconductor devices fabricated on the semiconductor chips, respectively, may be suppressed.

First claim

What is claimed is:

1 . A power module, comprising:
a first semiconductor chip that has a first side extending in a first direction and in which a first gate pad and a first another pad are provided along the first side; a second semiconductor chip that has a second side extending in the first direction and in which a second gate pad and a second another pad are provided along the second side, the second semiconductor chip being disposed adjacent to the first semiconductor chip in a second direction; a first wiring that is connected to the first gate pad and led to an outside of the first semiconductor chip across the first side; a second wiring that is connected to the second gate pad and led to an outside of the second semiconductor chip across the second side; a third wiring that is connected to the first another pad and led to the outside of the first semiconductor chip across the first side; and a fourth wiring that is connected to the second another pad and led to the outside of the second semiconductor chip across the second side.

2 . The power module according to claim 1 , wherein the first semiconductor chip and the second semiconductor chip respectively include a current sensing portion, and the first another pad and the second another pad are pads that are respectively connected to the current sensing portion of the first semiconductor chip and the current sensing portion of the second semiconductor chip.

3 . The power module according to claim 1 , wherein
the first semiconductor chip has a third another pad provided side by side with the first gate pad and the first another pad along the first side, and the second semiconductor chip has a fourth another pad provided side by side with the second gate pad and the second another pad along the second side.

4 . The power module according to claim 3 , wherein the first semiconductor chip and the second semiconductor chip respectively include a temperature sensing portion, and the third another pad and the fourth another pad are pads that are respectively connected to the temperature sensing portion of the first semiconductor chip and the temperature sensing portion of the second semiconductor chip.

5 . The power module according to claim 3 , wherein
the third another pad is located between the first gate pad and the first another pad in the first direction, and the fourth another pad is located between the second gate pad and the second another pad in the first direction.

6 . The power module according to claim 1 , wherein the first wiring, the second wiring, the third wiring, and the fourth wiring are wires.

7 . The power module according to claim 1 , further comprising:
a first metal pattern to which the first wiring is connected; and a second metal pattern to which the second wiring is connected.

8 . The power module according to claim 7 , wherein
the third wiring is connected to the first metal pattern, and the fourth wiring is connected to the second metal pattern.

9 . The power module according to claim 1 , wherein
the first semiconductor chip, the first wiring, and the second wiring have line symmetry with the second semiconductor chip, the third wiring, and the fourth wiring with respect to an axis extending in the first direction.

10 . The power module according to claim 1 , further comprising a first insulated substrate having a front surface on which the first semiconductor chip, the second semiconductor chip, the first wiring, the second wiring, the third wiring, and the fourth wiring are disposed.

11 . The power module according to claim 10 , further comprising a third semiconductor chip, a fourth semiconductor chip, a fifth wiring, a sixth wiring, a seventh wiring, an eighth wiring, and a second insulated substrate that have configurations identical to those of the first semiconductor chip, the second semiconductor chip, the first wiring, the second wiring, the third wiring, the fourth wiring, and the first insulated substrate, respectively.

12 . The power module according to claim 1 , wherein each of the first semiconductor chip and the second semiconductor chip is provided in plurality.

13 . The power module according to claim 12 , further comprising:
a ninth wiring that connects source pads of the first semiconductor chips; and a tenth wiring that connects source pads of the second semiconductor chips.

Assignees

• Fuji Electric Co Ltd

Inventors

• Hoshi Yasuyuki

Classifications

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10W72/5473

  multiple bond wires connected to a common bond pad · CPC title

• H10W72/521

  Structures or relative sizes of bond wires · CPC title

• H10W72/07552

  changes in structures or sizes · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title