Memory and method of accessing the memory

Patent metadata

Field	Value
Publication number	US-2025124976-A1
Application number	US-202418893493-A
Country	US
Kind code	A1
Filing date	Sep 23, 2024
Priority date	Oct 12, 2023
Publication date	Apr 17, 2025
Grant date	—

Abstract

A memory includes at least one memory bank which includes a set of memory arrays. Each memory cell includes a plurality of memory cells. The at least one memory bank includes: multiple word lines each connected to a corresponding row of the memory cells; a first decoder configured to receive address data, and decode the address data to provide intermediate data; a second decoder located in a central area of the memory bank between ones of the set of memory arrays, and configured to receive the intermediate data from the first decoder, and decode the intermediate data to provide selection data to the word lines. Memory cells addressable by a respective word line designated by the selection data are configured to be addressable by means of that selection data.

First claim

We claim:

1 . A memory comprising at least one memory bank comprising a set of memory arrays each comprising a plurality of memory cells; wherein the at least one memory bank comprises:
multiple word lines each connected to a corresponding row of the memory cells; a first decoder configured to receive address data, and decode the address data to provide intermediate data; and a second decoder located in a central area of the memory bank between ones of the set of memory arrays, and configured to receive the intermediate data from the first decoder, and decode the intermediate data to provide selection data to the word lines; wherein memory cells addressable by a respective word line designated by the selection data are configured to be addressable by means of that selection data.

2 . The memory of claim 1 , wherein the memory bank comprises eight memory arrays arranged in an array of 2 columns by 4 rows, and wherein the first decoder is placed at an edge of the memory bank between 2 columns of memory arrays, and the second decoder is placed between the second and third rows of the 4-row memory arrays.

3 . The memory of claim 1 , wherein each memory array comprises 8 rows each having 2048 memory cells.

4 . The memory of claim 1 , wherein the first decoder is configured to decode predetermined bits of the address data, wherein the predetermined bits are less in number than a total number of bits of the address data.

5 . The memory of claim 1 , wherein the first decoder comprises multiple sub-decoders each configured to decode segmented bits of the address data.

6 . The memory of claim 5 , wherein the sub-decoder of the first decoder is selected from a 2-to-4decoder and a 3-to-8 decoder.

7 . The memory of claim 1 , wherein the second decoder is configured to provide the selection data as a one-hot code decoded from the address data.

8 . The memory of claim 1 , wherein each memory bank further comprises a column multiplexer configured to access a one of the row of memory cells designated by the selection data, in response to a column address data.

9 . The memory of claim 1 , wherein each memory bank further comprises:
multiple bit lines each connected to a corresponding column of the memory cells; a column decoder configured to receive column address data and decode to provide column selection data to the bit lines; wherein memory cells addressable by a respective bit line designated by the column selection data are configured to be addressable by means of that column selection data.

10 . The memory of claim 1 , wherein the first decoder is further configured to receive control data, and decode the control data to control operation of the memory bank.

11 . A method of accessing a memory comprising at least one memory bank, the method comprising:
receiving, at a first decoder, address data for accessing the memory; wherein the at least one memory bank of the memory comprises a set of memory arrays each comprising a plurality of memory cells; decoding, by the first decoder, the address data, to provide intermediate data; receiving, by a second decoder located in a central area of the memory bank between ones of the set of memory arrays, the intermediate data from the first decoder; and decoding, by the second decoder, the intermediate data, to provide selection data to word lines each connected to a corresponding row of the memory cells; and enabling at least one of read or write access to the row of the memory cells connected to the word line designated by the selection data.

12 . The method of claim 11 , the memory bank comprises eight memory arrays arranged in an array of 2 columns by 4 rows, and wherein the first decoder is placed at an edge of the memory bank between 2 columns of memory arrays, and the second decoder is placed between the second and third rows of the 4-row memory arrays.

13 . The method of claim 11 , wherein each memory array comprises 8 rows each having 2048 memory cells.

14 . The method of claim 11 , wherein the decoding, by the first decoder, the address data, to provide intermediate data comprises decoding predetermined bits of the address data, the predetermined bits are less in number than a total number of bits of the address data.

15 . The method of claim 11 , wherein decoding, by the first decoder, the address data, to provide intermediate data comprises: at multiple sub-decoders of the first decoder, decoding segmented bits of the address data.

16 . The method of claim 15 , wherein the sub-decoder of the first decoder is selected from a 2-to-4 decoder and a 3-to-8 decoder.

17 . The method of claim 11 , wherein the decoding, by the second decoder, the intermediate data, to provide selection data comprises providing the selection data as a one-hot code decoded from the address data.

18 . The method of claim 11 , further comprising:
receiving, at a column multiplexer, column address data; accessing a one of the row of memory cells designated by the selection data, in response to the column address data.

19 . The method of claim 11 , further comprising:
receiving, at a column decoder, column address data; decoding, by the column decoder, the column address data, to provide column selection data to bit lines each connected to a corresponding column of the memory cells; and enabling at least one of read or write access to the column of the memory cells connected to the bit line designated by the column selection data.

20 . The method of claim 11 , further comprising:
receiving, at the first decoder, control data; decoding, by the first decoder, the control data, to control operation of the memory bank.

Assignees

• Nxp Bv

Inventors

• Singh Jainendra
• Kohli Rajat
• Bhat Ganesh
• Mishra Jwalant Kumar

Classifications

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C11/418 Primary

  Address circuits · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title