Computational storage acceleration using dram sharing between ssd in all-flash array

Patent metadata

Field	Value
Publication number	US-2025123772-A1
Application number	US-202318486318-A
Country	US
Kind code	A1
Filing date	Oct 13, 2023
Priority date	Oct 13, 2023
Publication date	Apr 17, 2025
Grant date	—

Abstract

A method for accelerating computational storage in an all-flash-array that comprises a plurality of solid state drives (SSDs) connected in a ring topology. The method includes receiving, by a controller of a first SSD, a request to read or write data from a dynamic random access memory (DRAM) associated with the first SSD, creating a packet that includes an identifier for the first SSD in the ring topology, an identifier for the packet, and a read/write flag that identifies the request, and transmitting the packet to a next SSD in the ring topology. When the request is a read request and a read data address is not located in the DRAM, the read/write flag indicates a read-request, and when the request is a write request and the DRAM is full, the read/write flag indicates a write-request, and the packet includes data to be written.

First claim

What is claimed is:

1 . A method for accelerating computational storage in an all-flash-array network that comprises a plurality of solid state drives (SSDs) connected in a ring topology, wherein each SSD of the plurality of SSDs includes a controller and a dynamic random access memory (DRAM) connected to the controller, the method comprising:
receiving, by a controller of a first SSD, a request to read or write data from a DRAM associated with the first SSD; creating a packet that includes an identifier for the first SSD in the ring topology, an identifier for the packet, and a read/write flag that identifies the request; and transmitting the packet to a next SSD in the ring topology, wherein the read/write flag indicates a read-request, in response to the request being a read request and a read data address being not located in the DRAM, and the read/write flag indicates a write request, and the packet includes data to be written, in response to the request being a write request and the DRAM being full.

2 . The method of claim 1 , further comprising:
verifying that the read/write flag indicates a read request and a read data address is located in the DRAM, and reading data from the read data address in the DRAM.

3 . The method of claim 1 , further comprising: verifying that the read/write flag indicates a write request and the DRAM is not full, and
writing data to a write address in the DRAM.

4 . The method of claim 1 , further comprising:
receiving, by the next SSD in the ring topology, the packet; verifying that the next SSD in the ring topology differs from the first SSD in the ring topology, the read/write flag indicates a write-request and a DRAM associated with the next SSD is not full; requesting a write address for a DRAM associated with the next SSD from a controller of the next SSD; writing the data in the packet to the write address for the DRAM; updating the packet by setting the read/write flag to indicate a write-acknowledgement; and transmitting the packet to a next SSD in the ring topology.

5 . The method of claim 1 , further comprising:
receiving, by the next SSD in the ring topology, the packet; verifying that the next SSD in the ring topology differs from the first SSD in the ring topology, and the read/write flag indicates a read-request; requesting a read address for a DRAM associated with the next SSD from a controller of the next SSD, based on the identifier for the first SSD in the ring topology and the identifier of the packet; updating the packet by setting the read/write flag to indicate a write-acknowledgement, and replacing the data to be written with data read from the read-address; and transmitting the packet to a next SSD in the ring topology.

6 . The method of claim 1 , further comprising:
receiving, by the next SSD in the ring topology, the packet; verifying that the next SSD in the ring topology is the first SSD in the ring topology; updating incoming/outgoing packet tables of the controller of the first SSD, in response to the read/write flag indicating a write-acknowledgement; performing a DRAM out-of-space procedure, in response to the read/write flag indicating a write-request and the DRAM associated with the first SSD is full; and outputting the data of the packet to a host of the all-flash array, in response to the read/write flag indicating a read-acknowledgement.

7 . The method of claim 1 , wherein the packet includes fields for an SSD identifier, an identifier for the packet, a read/write request/acknowledge flag, and data to be either written to the a DRAM associated with an SSD or read from a DRAM associated with an SSD.

8 . An architecture for accelerating computational storage in an all-flash-array, comprising:
a plurality of solid state drives (SSDs) connected to an input/output (I/O) hub, wherein each SSD of the plurality of SSDs includes a controller, a DRAM connected to the controller, and a plurality of NAND memories connected to the controller, wherein the plurality of SSDs are connected in a ring topology in which each controller includes an input port and an output port, each input port of each SSD is connected by a connector to an output port of a predecessor SSD, and the input port of a first SSD of the plurality of SSDs is connected by a connector to the output port of a last SSD of the plurality of SSDs; and a processor connected to the hub.

9 . The architecture of claim 8 , wherein each SSD further includes a hardware accelerator connected to the DRAM, wherein the hardware accelerator accelerates tasks other than reading or writing to the DRAM of each SSD.

10 . The architecture of claim 8 , further comprising an artificial intelligence (AI) server, wherein the AI server is an SSD that includes a processor, a DRAM connected to the processor, and a plurality of NAND memories connected to the processor.

11 . The architecture of claim 8 , wherein the connector is a cable.

12 . The architecture of claim 8 , wherein the controller of each SSD comprises:
a DRAM manager connected to the DRAM and the output port; a packet buffer connected to the input port, the DRAM and the output port; an inter-SSD finite sate machine (FSM) connected to the packet buffer, the input port, and the DRAM manager, wherein the inter-SSD FSM performs packet routing and handling of received packets; a multiplexer that connects the DRAM manager and the packet buffer to the output port; a multiplexer that connects the DRAM manager and the packet buffer to the DRAM; and additional components that connect the DRAM manager to a host and to the NAND memories.

13 . The architecture of claim 12 , wherein the packet routing comprises:
receiving, by a controller of a first SSD, a request to read or write data from a DRAM associated with the first SSD, creating a packet that includes an identifier for the first SSD in the ring topology, an identifier for the packet, and a read/write flag that identifies the request; and transmitting the packet to a next SSD in the ring topology, wherein the read/write flag indicates a read-request, in response to the request being a read request and a read data address being not located in the DRAM, and the read/write flag indicates a write request, and the packet includes data to be written, in response to the request being a write request and the DRAM being full.

14 . The architecture of claim 12 , wherein the packet handling comprises:
receiving, by the next SSD in the ring topology, the packet; verifying that the next SSD in the ring topology differs from the first SSD in the ring topology, the read/write flag indicates a write-request and a DRAM associated with the next SSD is not full; requesting a write address for a DRAM associated with the next SSD from a controller of the next SSD; writing the data in the packet to the write address for the DRAM; updating the packet by setting the read/write flag to indicate a write-acknowledgement; and transmitting the packet to a next SSD in the ring topology.

15 . The architecture of claim 12 , wherein the packet handling comprises:
receiving, by the next SSD in the ring topology, the packet; verifying that the next SSD in the ring topology differs from the first SSD in the ring topology, and the read/write flag indicates a read-request; requesting a read address for a DRAM associated with the next SSD from a controller of the next SSD, based on the identifier for the first SSD in the ring topology and the identifier of the packet; updating the packet by setting the read/write flag to indicate a read-acknowledgement, and r

Assignees

• Samsung Electronics Co Ltd

Inventors

• Berman Amit

Classifications

• G06F2212/214

  Solid state disk · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F3/0604 Primary

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0689

  Disk arrays, e.g. RAID, JBOD · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title