Impedance calibration circuit and method

Patent metadata

Field	Value
Publication number	US-2025119121-A1
Application number	US-202418985370-A
Country	US
Kind code	A1
Filing date	Dec 18, 2024
Priority date	Mar 10, 2023
Publication date	Apr 10, 2025
Grant date	—

Abstract

An impedance calibration circuit includes a variable impedance circuit, a detection circuit and a control circuit. The variable impedance circuit includes conduction paths connected in parallel between an output terminal and a supply terminal coupled to a first supply voltage. The variable impedance circuit is configured to adjust an impedance at the output terminal by enabling one or more of the conduction paths according to a calibration code. The detection circuit is configured to detect a change in impedance of the conduction paths by applying a second supply voltage to a reference terminal through a detection path, and accordingly generate an input voltage at the reference terminal. An electric potential of the second supply voltage is equal to an electric potential of the first supply voltage. The control circuit is configured to compare the input voltage with reference voltages to generate the calibration code.

First claim

What is claimed is:

1 . An impedance calibration circuit, comprising:
a variable impedance circuit, comprising a plurality of conduction paths connected in parallel, each of the conduction paths being coupled to an output terminal, the variable impedance circuit being configured to adjust an impedance at the output terminal by enabling one or more of the conduction paths according to a calibration code; a first comparator, coupled to the variable impedance circuit, the first comparator being configured to compare an input voltage at the output terminal with a predetermined reference voltage to generate a first comparison result, the first comparison result serving as a first portion of the calibration code; and a signal generator circuit, coupled to the variable impedance circuit, the detection circuit and the first comparator, the signal generator circuit being configured to compare the input voltage with one set of reference voltages selected from among a first set of reference voltages and a second set of reference voltages according to the first comparison result, and accordingly generate a second portion of the calibration code, wherein the first set of reference voltages is different from the second set of reference voltages.

2 . The impedance calibration circuit of claim 1 , wherein each reference voltage in the first set of reference voltages is greater than the predetermined reference voltage, and each reference voltage in the second set of reference voltages is less than the predetermined reference voltage.

3 . The impedance calibration circuit of claim 1 , wherein:
the conduction paths comprise a conduction path, a first group of conduction paths and a second group of conductive paths; the conductive path and each conduction path in the first group of conduction paths are enabled; when the first comparison result indicates that the input voltage is less than the predetermined reference voltage, the variable impedance circuit is configured to selectively enable at least one conduction path in the second group of conduction paths according to the calibration code; and when the first comparison result indicates that the input voltage is greater than the predetermined reference voltage, the variable impedance circuit is configured to disable each conduction path in the second group of conduction paths, and selectively disable at least one conduction path in the first group of conduction paths according to the calibration code.

4 . The impedance calibration circuit of claim 1 , wherein:
the conduction paths comprise a first conduction path and a second conduction path, and an impedance of the first conduction path is different from an impedance of the second conduction path; the selected set of reference voltages comprises a first reference voltage, a second reference voltage and a third reference voltage; the second reference voltage is greater than the first reference voltage, and less than the third reference voltage; and when the input voltage is between the first reference voltage and the second reference voltage, the variable impedance circuit is configured to disable the first conduction path and enable the second conduction path; when the input voltage is between the second reference voltage and the third reference voltage, the variable impedance circuit is configured to enable the first conduction path and disable the second conduction path.

5 . The impedance calibration circuit of claim 4 , wherein when the input voltage is greater than the third reference voltage, the variable impedance circuit is configured to disable the first conduction path and the second conduction path.

6 . The impedance calibration circuit of claim 4 , wherein when the input voltage is less than the first reference voltage, the variable impedance circuit is configured to enable the first conduction path and the second conduction path.

7 . The impedance calibration circuit of claim 1 , wherein the signal generator circuit comprises:
N comparison circuits, coupled to N reference voltages in the first set of reference voltages respectively and coupled to N reference voltages in the second set of reference voltages respectively, N being an integer greater than one, wherein each comparison circuit is configured to compare the input voltage with a corresponding reference voltage in the selected set of reference voltages, and accordingly generate a second comparison result; and a processing circuit, coupled to the N comparison circuits, the processing circuit being configured to process the N second comparison results to generate the second portion of the calibration code.

8 . The impedance calibration circuit of claim 7 , wherein the comparison circuit comprises:
a first multiplexer, configured to output one of the input voltage and a corresponding reference voltage in the first set of reference voltages as a first voltage according to the first comparison result; a second multiplexer, configured to output one of the input voltage and a corresponding reference voltage in the second set of reference voltages as a second voltage according to the first comparison result; and a second comparator, coupled to the first multiplexer and the second multiplexer, the second comparator being configured to compare the first voltage with the second voltage to generate the second comparison result; wherein when the first multiplexer is configured to output the reference voltage in the first set of reference voltages as the first voltage, the second multiplexer is configured to output the input voltage as the second voltage; when the first multiplexer is configured to output the input voltage as the first voltage, the second multiplexer is configured to the reference voltage in the second set of reference voltages as the second voltage.

9 . The impedance calibration circuit of claim 1 , wherein the signal generator circuit comprises:
a selection stage, configured to select the one set of reference voltages from among the first set of reference voltages and the second set of reference voltages according to the first comparison result, and output the selected set of reference voltages; a comparison stage, coupled to the selection stage, the comparison stage being configured to compare the input voltage with each reference voltage in the selected one set of reference voltages to generate a set of second comparison results; and a processing circuit, coupled to the comparison stage, the processing circuit being configured to process the set of second comparison results to generate the second portion of the calibration code.

10 . The impedance calibration circuit of claim 1 , wherein:
the conduction paths comprise a conduction path, a first group of conduction paths and a second group of conduction paths; when the input voltage is less than a minimum voltage of the reference voltages, the variable impedance circuit is configured to enable the conductive path, each conduction path in the first group of conduction paths, and each conduction path in the second group of conduction paths; and when the input voltage is greater than a maximum voltage of the reference voltages, the variable impedance circuit is configured to enable the conductive path, disable each conduction path in the first group of conduction paths, and disable each conduction path in the second group of conduction paths.

11 . The impedance calibration circuit of claim 1 , wherein respective voltage differences between the predetermined reference voltage and each reference voltage in the first set of reference voltages are equal in magnitude to respective voltage differences between the predetermined reference voltage and each refere

Assignees

• M31 Tech Corp

Inventors

• Tsai Ming-Yen
• Chao Tze-Hsiang

Classifications

• H03K5/24

  the characteristic being amplitude · CPC title

• G11C7/1048

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G11C2207/2254

  Calibration · CPC title

• H03K19/0005

  Modifications of input or output impedance · CPC title

• G11C29/50008

  of impedance · CPC title