Tamper sensor for 3-dimensional die stack

Patent metadata

Field	Value
Publication number	US-2025111765-A1
Application number	US-202318374639-A
Country	US
Kind code	A1
Filing date	Sep 28, 2023
Priority date	Sep 28, 2023
Publication date	Apr 3, 2025
Grant date	—

Abstract

An integrated circuit die stack and method thereof are described herein that is capable of detecting a physical tampering event. The integrated circuit die stack includes a first integrated circuit die including a sensor network that extends substantially across an entire top surface of the first integrated circuit die, and a second integrated circuit die stacked below the first integrated circuit die. The second integrated circuit die is configured to receive sensing signals generated by the sensor network via a plurality of through-silicon-vias coupled with the first integrated circuit die and the second integrated circuit die.

First claim

What is claimed is:

1 . An integrated circuit die stack comprising:
a first integrated circuit die comprising a sensor network that extends substantially across an entire top surface of the first integrated circuit die; and a second integrated circuit die stacked below the first integrated circuit die and configured to receive sensing signals generated by the sensor network via a plurality of through-silicon-vias that are coupled with the first integrated circuit die and the second integrated circuit die.

2 . The integrated circuit die stack according to claim 1 , wherein the sensor network comprises a plurality of addressable memory banks arranged across a layer parallel to a plane of a top surface of the first integrated circuit die.

3 . The integrated circuit die stack according to claim 2 , wherein the plurality of addressable memory banks are arranged in an array, and the addressable memory banks in a same row or column are serially connected.

4 . The integrated circuit die stack according to claim 2 , wherein at least one of the plurality of addressable memory banks comprises a plurality of shift registers.

5 . The integrated circuit die stack according to claim 4 , wherein the plurality of shift registers are connected in parallel.

6 . The integrated circuit die stack according to claim 5 , wherein each shift register comprises a plurality of serially connected flip-flops.

7 . The integrated circuit die stack according to claim 6 , wherein each shift register comprises a first input operable to receive a clock signal, a second input operable to receive a data signal, a third input operable to receive an activation signal, and a tri-state buffer coupled with the activation signal.

8 . The integrated circuit die stack according to claim 1 , further comprising a third integrated circuit die disposed between the first integrated circuit die and the second integrated circuit die.

9 . The integrated circuit die stack according to claim 8 , wherein the plurality of through-silicon-vias are coupled with the third integrated circuit die.

10 . The integrated circuit die stack according to claim 1 , wherein the first integrated circuit die further comprises a first reading circuitry disposed in a first peripheral area of the first integrated circuit die.

11 . The integrated circuit die stack according to claim 10 , wherein the second integrated circuit die further comprises a second reading circuitry disposed in a second peripheral area of the second integrated circuit die.

12 . The integrated circuit die stack according to claim 11 , wherein the first reading circuitry and the second reading circuitry are coupled with the plurality of through-silicon-vias.

13 . The integrated circuit die stack according to claim 10 , wherein the first reading circuitry is configured to read the sensor network along one direction.

14 . The integrated circuit die stack according to claim 13 , wherein the first reading circuitry is configured to read the sensor network along two opposite directions.

15 . A method for detecting a tampering event of an integrated circuit die stack, comprising:
transmitting a probing signal from a second integrated circuit die to a sensor network disposed in a first integrated circuit die, the first integrated circuit die comprising an input/output interface disposed around a peripheral area of the first integrated circuit die; routing the probing signal through a plurality of addressable memory banks of the sensor network; reading, by the input/output interface, a sensing signal output by the plurality of addressable memory banks generated based on the probing signal; and providing the sensing signal to the second integrated circuit die via a plurality of through-silicon-vias, the second integrated circuit die stacked below the first integrated circuit die and configured to determine the tampering event based on the sensing signal.

16 . The method according to claim 15 , wherein inputting the probing signal to the sensor network occurs during a reboot of the integrated circuit die stack.

17 . The method according to claim 16 , wherein inputting the probing signal to the sensor network occurs during a runtime of the integrated circuit die stack.

18 . The method according to claim 15 , wherein the first input/output interface reads the sensing signal in two opposite directions.

19 . The method according to claim 15 , further comprising:
determining a location of the tampering event based on the sensing signal.

20 . The method according to claim 15 , further comprising:
attaching a column address and/or a row address to the sensing signal.

Assignees

• Xilinx Inc

Inventors

• Leboeuf Thomas Paul
• Anderson James
• Wesselkamper James D
• Moore Jason J

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/247

  Dispositions of multiple bumps · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title