Wide-range power delivery system

Patent metadata

Field	Value
Publication number	US-2025105734-A1
Application number	US-202418895180-A
Country	US
Kind code	A1
Filing date	Sep 24, 2024
Priority date	Sep 25, 2023
Publication date	Mar 27, 2025
Grant date	—

Abstract

Power delivery systems for integrated circuits that include a first metal path traversing first metal layers from a global power domain supply to a voltage regulator, a second metal path traversing second metal layers from a local power domain supply to the voltage regulator, and a third metal path traversing third metal layers from the local power domain supply to an integrated circuit. Electrical isolation gaps are formed between the first metal layers, the second metal layers, and the third metal layers.

First claim

What is claimed is:

1 . A power delivery system comprising:
a global power domain supply; a local power domain supply; a first metal path traversing first metal layers from the global power domain supply to a voltage regulator; a second metal path traversing second metal layers from the local power domain supply to the voltage regulator; a third metal path traversing third metal layers from the local power domain supply to an integrated circuit; and electrical isolation gaps formed between the first metal layers, the second metal layers, and the third metal layers.

2 . The power delivery system of claim 1 , the voltage regulator configured to electrically couple the first metal layers to the second metal layers.

3 . The power delivery system of claim 1 , wherein each of the first metal layers, the second metal layers, and the third metal layers comprise progressively thinner metal layers.

4 . The power delivery system of claim 1 , further comprising:
a fourth metal path traversing fourth metal layers from the global power domain supply to a power gate.

5 . The power delivery system of claim 4 , the power gate configured to electrically couple the fourth metal layers to the third metal layers.

6 . The power delivery system of claim 5 , the power gate configured to electrically couple a lowest of the fourth metal layers to a lowest of the third metal layers.

7 . The power delivery system of claim 4 , further comprising electrical isolation gaps formed between the fourth metal layers and the first metal layers, the second metal layers, and the third metal layers.

8 . The power delivery system of claim 1 , further comprising:
a retention circuit coupled between the first metal layers and the second metal layers.

9 . The power delivery system of claim 8 , wherein the retention circuit is coupled in parallel with the voltage regulator.

10 . The power delivery system of claim 9 , wherein the retention circuit comprises a plurality of diode stacks arranged in parallel.

11 . The power delivery system of claim 1 , wherein the regulator comprises a complementary self-biased differential comparator.

12 . An integrated circuit power delivery network comprising:
a plurality of voltage regulators arranged in the integrated circuit in a grid layout; a plurality of reference voltage generators interspersed among the voltage regulators, each reference voltage generator configured to provide a reference voltage level to multiple ones of the plurality of voltage regulators; a first metal path traversing first metal layers from a global power supply to the voltage regulators; a second metal path traversing second metal layers from a local power supply to the voltage regulators; a third metal path traversing third metal layers from the local power supply to logic cells of the integrated circuit; and electrical isolation gaps formed between the first metal layers, the second metal layers, and the third metal layers.

13 . The power delivery network of claim 12 , wherein the reference voltage generators operate solely from the global power supply.

14 . The power delivery network of claim 12 , the voltage regulators configured to electrically couple a lowest layer of first metal layers to a lowest layer of the second metal layers.

15 . The power delivery network of claim 12 , wherein each of the first metal layers, the second metal layers, and the third metal layers comprise progressively thinner metal layers.

16 . The power delivery network of claim 12 , further comprising:
a fourth metal path traversing fourth metal layers from the global power domain supply to a plurality of power gates.

17 . The power delivery network of claim 16 , the power gates configured to electrically couple the fourth metal layers to the third metal layers.

18 . The power delivery network of claim 17 , the power gates configured to electrically couple a lowest metal layer of the fourth metal layers to a lowest metal layer of the third metal layers.

19 . The power delivery network of claim 16 , further comprising electrical isolation gaps formed between the fourth metal layers and the first metal layers, the second metal layers, and the third metal layers.

20 . The power delivery network of claim 12 , further comprising:
a plurality of retention circuits coupled between the first metal layers and the second metal layers.

21 . The power delivery network of claim 20 , wherein the retention circuits are coupled in parallel with the voltage regulators.

22 . The power delivery network of claim 21 , wherein the retention circuits each comprise a plurality of diode stacks arranged in parallel.

23 . The power delivery network of claim 12 , wherein the regulators each comprise a complementary self-biased differential comparator.

24 . A system configured to operate an integrated circuit in a plurality of power modes, the system comprising:
a circuit die comprising a plurality of logic cells, a plurality of voltage regulators, a plurality of power gates, and a plurality of retention circuits; a power delivery network comprising: a first metal path traversing first metal layers from a global power supply to the voltage regulators and the retention circuits; a second metal path traversing second metal layers from a local power supply to the voltage regulators and the retention circuits; a third metal path traversing third metal layers from the local power supply to the logic cells of the integrated circuit; a fourth metal path traversing fourth metal layers from the global power supply to the power gates; and electrical isolation gaps formed between the first metal layers, the second metal layers, the third metal layers, and the fourth metal layers.

Assignees

• Nvidia Corp

Inventors

• Saxena Siddharth
• Kudva Sudhir Shrikantha
• Rodriguez Miguel
• Srinivasan Vijay
• Raja Tezaswi
• Gray Carl Thomas
• Santosh Santosh

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/427

  Power or ground buses · CPC title

• G04F10/005

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• G05F1/56 Primary

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title

• H03M7/165 Primary

  Conversion to or from thermometric code · CPC title