Voltage regulator partitioning across stacked die

Patent metadata

Field	Value
Publication number	US-2025103074-A1
Application number	US-202318474147-A
Country	US
Kind code	A1
Filing date	Sep 25, 2023
Priority date	Sep 25, 2023
Publication date	Mar 27, 2025
Grant date	—

Abstract

Embodiments herein relate to a voltage regular (VR) formed from dies stacked on a package base layer. The VR can include a first part on a first die and a second part on a second die, where the different parts are selected based on characteristics of the respective die such as their voltage domains or technologies. In a capacitor-based VR, an input capacitor and switches subject to a relatively high input voltage can be provided in the first die, while a flying capacitor, output capacitor and switches subject to a relatively low output voltage can be provided in the second die. In an inductor-based VR, an inductor and one or more switches subject to a relatively high input voltage can be provided in the first die, while an output capacitor subject to a relatively low output voltage can be provided in the second die.

First claim

What is claimed is:

1 . An apparatus, comprising:
a first die; a second die stacked on the first die; and a voltage regulator comprising a first part on the first die and a second part on the second die, wherein the first part comprises an input node and the second part comprises an output node.

2 . The apparatus of claim 1 , further comprising a package base layer on which the first die is stacked, wherein the package base layer comprises a third part of the voltage regulator.

3 . The apparatus of claim 1 , further comprising one or more additional voltage regulators on the second die, wherein the output node is coupled to the one or more additional voltage regulators.

4 . The apparatus of claim 1 , wherein:
the first part of the voltage regulator comprises an input capacitor coupled to the input node, a first switch coupled to a first side of the input capacitor and a second switch coupled to a second side of the input capacitor; and the second part of the voltage regulator comprises a flying capacitor, a third switch coupled to a first side of the flying capacitor and a fourth switch coupled to a second side of the flying capacitor.

5 . The apparatus of claim 1 , wherein:
the first part of the voltage regulator comprises a switch coupled to the input node, and an inductor coupled to the switch; and the second part of the voltage regulator comprises an output capacitor coupled to the inductor.

6 . The apparatus of claim 1 , further comprising a package base layer on which the first die is stacked, wherein:
the package base layer comprises a third part of the voltage regulator; the first part of the voltage regulator comprises a switch coupled to the input node; the third part of the voltage regulator comprises an inductor coupled to the switch; and the second part of the voltage regulator comprises an output capacitor coupled to the inductor.

7 . The apparatus of claim 1 , wherein:
the first part of the voltage regulator comprises a high-side switch coupled to the input node, a low-side switch coupled to the input node, and an inductor coupled to the high-side switch and the low-side switch; and the second part of the voltage regulator comprises an output capacitor coupled to the inductor.

8 . The apparatus of claim 1 , further comprising a package base layer on which the first die is stacked, wherein:
the package base layer comprises a third part of the voltage regulator; the first part of the voltage regulator comprises a high-side switch coupled to the input node and a low-side switch coupled to the input node; the third part of the voltage regulator comprises an inductor coupled to the high-side switch and the low-side switch; and the second part of the voltage regulator comprises an output capacitor coupled to the inductor.

9 . The apparatus of claim 1 , wherein the first part of the voltage regulator is in a higher voltage domain than a voltage domain of the second part of the voltage regulator.

10 . The apparatus of claim 1 , further comprising at least one of an integrated circuit, a System on Chip, a System in Package or a computing device in which the first die, second die and voltage regulator are provided, wherein the computing device comprises at least one of a processor circuitry, a memory circuitry, a storage circuitry, an acceleration circuitry, a communication circuitry, an input circuitry, an output circuitry, an interface circuitry or an external device.

11 . The apparatus of claim 1 , wherein the first part comprises an inductor-based voltage converter and the second part comprises a switched-capacitor-based voltage converter.

12 . A voltage regulator, comprising:
one or more active devices having a first voltage blocking capability; one or more active devices having a second voltage blocking capability, different than the first voltage blocking capability, wherein the one or more active devices having the first voltage blocking capability are on a first die in a stack, and the one or more active devices having the second voltage blocking capability are on a second die in the stack; and conductive points between the first and second die to couple the one or more active devices having the first voltage blocking capability to the one or more active devices having the second voltage blocking capability.

13 . The voltage regulator of claim 12 , wherein:
the first voltage blocking capability is greater than the second voltage blocking capability; and a voltage domain of the first die is greater than a voltage domain of the second die.

14 . The voltage regulator of claim 12 , further comprising an inductor coupled to the one or more active devices having the first voltage blocking capability.

15 . The voltage regulator of claim 14 , wherein the inductor is in the first die or in a package base layer of the stack.

16 . The voltage regulator of claim 12 , further comprising:
an input capacitor coupled to the one or more active devices having the first voltage blocking capability; and a flying capacitor coupled to the one or more active devices having the second voltage blocking capability.

17 . The voltage regulator of claim 12 , further comprising an input capacitor coupled to the one or more active devices having the first voltage blocking capability and an output capacitor coupled to the one or more active devices having the second voltage blocking capability.

18 . An apparatus, comprising:
a first die; a second die stacked on the first die; a voltage regulator comprising a first part on the first die and a second part on the second die; a controller for the voltage regulator, wherein the controller is on the first die and is coupled to the first part and to the second part; and fuses coupled to the controller, wherein the fuses are on the first die.

19 . The apparatus of claim 18 , wherein an output node of the voltage regulator is coupled to one or more additional voltage regulators on the second die.

20 . The apparatus of claim 18 , wherein a voltage domain of the first die is greater than a voltage domain of the second die.

Assignees

• Intel Corp

Inventors

• Krishnamurthy Harish K
• Butzen Nicolas
• Ahmed Khondker
• Desai Nachiket
• Kim Su Hwan
• Ravichandran Krishnan
• Radhakrishnan Kaladhar
• Douglas Jonathan

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10D1/20

  Inductors · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M3/072

  adapted to generate an output voltage whose value is lower than the input voltage · CPC title