Integrated circuit devices and methods of manufacturing the same

US2025098186A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2025098186-A1
Application numberUS-202418966548-A
CountryUS
Kind codeA1
Filing dateDec 3, 2024
Priority dateJun 24, 2021
Publication dateMar 20, 2025
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An integrated circuit (IC) device includes a lower electrode including a first metal, a dielectric film on the lower electrode, and a conductive interface layer between the lower electrode and the dielectric film. The conductive interface layer includes a metal oxide film including at least one metal element. An upper electrode including a second metal is opposite the lower electrode, with the conductive interface layer and the dielectric film therebetween. To manufacture an IC device, an electrode including a metal is formed adjacent to an insulating pattern on a substrate. A conductive interface layer including a metal oxide film including at least one metal element is selectively formed on a surface of the electrode. A dielectric film is formed to be in contact with the conductive interface layer and the insulating pattern.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method of manufacturing an integrated circuit device, the method comprising: forming an insulating pattern on a substrate; forming an electrode adjacent to the insulating pattern on the substrate, the electrode comprising a metal; selectively forming a conductive interface layer on a surface of the electrode, the conductive interface layer comprising a metal oxide film comprising at least one metal element; and forming a dielectric film in contact with the conductive interface layer and the insulating pattern. 2 . The method of claim 1 , wherein the selectively forming of the conductive interface layer comprises: forming a first interface sub-layer in contact with the surface of the electrode, the first interface sub-layer comprising a first metal element; and forming a second interface sub-layer in contact with the first interface sub-layer, the second interface sub-layer comprising a second metal element that is different from the first metal element. 3 . The method of claim 1 , wherein the selectively forming of the conductive interface layer comprises: performing a deposition inhibition treatment on a surface of the insulating pattern, from among the electrode and the insulating pattern, by supplying a first pre-processing gas for selectively inhibiting deposition onto a resultant structure in which the insulating pattern and the electrode are exposed; selectively forming an adsorption layer of a first precursor comprising a first metal element only on the surface of the electrode, from among the insulating pattern that has been treated to inhibit deposition and the electrode, by supplying the first precursor to the insulating pattern that has been treated to inhibit deposition and the electrode; and forming a first metal oxide film comprising the first metal element from the adsorption layer of the first precursor by supplying a first oxidizing gas onto a resultant structure comprising the adsorption layer of the first precursor. 4 . The method of claim 3 , wherein the first pre-processing gas comprises H 2 , N 2 , Ar, O 2 , O 3 , H 2 O, NH 3 , a silicon-containing organic compound, a phosphorus-containing organic compound, a sulfur-containing organic compound, a halogen element-containing organic compound, a nitrogen-containing organic compound, a hydroxyl-containing organic compound, organo aminosilane, or a combination thereof. 5 . The method of claim 3 , wherein the first metal element comprises aluminum (Al), zirconium (Zr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), indium (In), tin (Sn), antimony (Sb), scandium (Sc), titanium (Ti), vanadium (V), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), arsenic (As), tantalum (Ta), tungsten (W), iridium (Ir), yttrium (Y), or bismuth (Bi). 6 . The method of claim 3 , wherein the first oxidizing gas comprises O 2 , O 3 , H 2 O, NO 2 , NO, nitrous oxide (N 2 O), CO, CO 2 , H 2 O 2 , HCOOH, CH 3 COOH, (CH 3 CO) 2 O, alcohols, peroxides, sulfur oxide, plasma O 2 , remote plasma O 2 , plasma N 2 O, plasma H 2 O, or a combination thereof. 7 . The method of claim 3 , after the forming of the first metal oxide film, further comprising: performing a deposition inhibition treatment on a surface of the insulating pattern, from among the first metal oxide film and the insulating pattern, by supplying a second pre-processing gas for selectively inhibiting deposition onto a resultant structure in which the insulating pattern and the first metal oxide film are exposed, and wherein the second pre-processing gas comprises H 2 , N 2 , Ar, O 2 , O 3 , H 2 O, NH 3 , a silicon-containing organic compound, a phosphorus-containing organic compound, a sulfur-containing organic compound, a halogen element-containing organic compound, a nitrogen-containing organic compound, a hydroxyl-containing organic compound, organo aminosilane, or a combination thereof. 8 . The method of claim 3 , wherein the selectively forming of the conductive interface layer further comprises: after the forming of the first metal oxide film, performing a deposition inhibition treatment on a surface of the insulating pattern, from among the first metal oxide film and the insulating pattern, by supplying a second pre-processing gas for selectively inhibiting deposition onto a resultant structure in which the insulating pattern and the first metal oxide film are exposed; selectively forming an adsorption layer of a second precursor comprising a second metal element only on a surface of the first metal oxide film, from among the insulating pattern that has been treated to inhibit deposition and the first metal oxide film, by supplying the second precursor to the insulating pattern that has been treated to inhibit deposition and the first metal oxide film, wherein the second metal element is different from the first metal element; and forming a second metal oxide film comprising the second metal element from the adsorption layer of the second precursor by supplying a second oxidizing gas onto a resultant structure in which the adsorption layer of the second precursor is formed. 9 . The method of claim 1 , after the selectively forming of the conductive interface layer and before the forming of the dielectric film, further comprising densifying the conductive interface layer by supplying a post-processing gas to the conductive interface layer, wherein the post-processing gas comprises a material comprising H 2 , N 2 , Ar, O 2 , O 3 , H 2 O, NH 3 , or a combination thereof. 10 . The method of claim 1 , wherein the selectively forming of the conductive interface layer comprises forming at least three interface sub-layers, and wherein, from among the at least three interface sub-layers, two interface sub-layers that are in contact with each other comprise different respective metal elements. 11 . The method of claim 1 , wherein the metal included in the electrode comprises a different material from the at least one metal element included in the conductive interface layer. 12 . The method of claim 1 , wherein the at least one metal element included in the conductive interface layer comprises a same element as the metal included in the electrode. 13 . A method of manufacturing an integrated circuit device, the method comprising: forming a lower electrode and an insulating support pattern on a substrate, the lower electrode comprising a first metal, the insulating support pattern being configured to support the lower electrode; selectively forming a conductive interface layer only on a surface of the lower electrode, from among the insulating support pattern and the lower electrode, the conductive interface layer comprising a metal oxide film comprising at least one metal element; densifying the conductive interface layer by supplying a post-processing gas to the conductive interface layer; forming a dielectric film in contact with the conductive interface layer and the insulating support pattern; and forming an upper electrode opposite the lower electrode with the conductive interface layer and the dielectric film therebetween, the upper electrode comprising a second metal. 14 . The method of claim 13 , wherein the selectively forming of the conductive interface layer comprises forming at least three interface sub-layers, and wherein, from among the at least three interface sub-layers, two interface sub-layers that are in contact with each other comprise different respective metal elements. 15 . The method of claim 13 , wherein the at least one metal element comprises aluminum (Al), zirconium (Zr), niobium (Nb), molybdenum (Mo), rutheni

Assignees

Inventors

Classifications

  • the capacitor extending over the transistor · CPC title

  • having a storage electrode stacked over the transistor · CPC title

  • H10D1/696Primary

    comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

  • the transistor being at least partially in a trench in the substrate · CPC title

  • characterised by multiple passive components, e.g. resistors, capacitors or inductors · CPC title

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What does patent US2025098186A1 cover?
An integrated circuit (IC) device includes a lower electrode including a first metal, a dielectric film on the lower electrode, and a conductive interface layer between the lower electrode and the dielectric film. The conductive interface layer includes a metal oxide film including at least one metal element. An upper electrode including a second metal is opposite the lower electrode, with the …
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D1/696. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Mar 20 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).