Integrated circuit including complementary field effect transistor

Patent metadata

Field	Value
Publication number	US-2025096138-A1
Application number	US-202418739664-A
Country	US
Kind code	A1
Filing date	Jun 11, 2024
Priority date	Sep 19, 2023
Publication date	Mar 20, 2025
Grant date	—

Abstract

Provided is an integrated circuit including a complementary field effect transistor including a first transistor and a second transistor arranged in a vertical direction on a front side of a substrate, a via structure extending in the vertical direction on the second transistor and interconnecting a source/drain of the second transistor to a source/drain of the first transistor, at least one frontside power rail disposed above the first transistor in the vertical direction and transmitting a first supply voltage to the first transistor, a backside via penetrating through the substrate in the vertical direction, and at least one backside power rail disposed on a back side of the substrate and transmitting a second supply voltage to the second transistor through the backside via, wherein the first supply voltage and the second supply voltage have different voltage levels, and the first transistor and the second transistor share a gate line.

First claim

What is claimed is:

1 . An integrated circuit comprising:
a complementary field effect transistor comprising a first transistor and a second transistor arranged in a vertical direction on a front side of a substrate; a via structure extending in the vertical direction on the second transistor and connecting the second transistor to the first transistor; at least one frontside power rail above the first transistor in the vertical direction and configured to transmit a first supply voltage to the first transistor; a backside via penetrating through the substrate in the vertical direction; and at least one backside power rail on a back side of the substrate and configured to transmit a second supply voltage to the second transistor through the backside via, wherein the first supply voltage and the second supply voltage are different, and wherein the first transistor and the second transistor share a gate line.

2 . The integrated circuit of claim 1 ,
wherein the at least one backside power rail comprises a first backside power rail and a second backside power rail, each below the complementary field effect transistor in the vertical direction and extending in a first direction, wherein the at least one frontside power rail comprises a first frontside power rail and a second frontside power rail, each above the complementary field effect transistor in the vertical direction and extending in the first direction, wherein the first transistor is configured to receive the first supply voltage from the first frontside power rail and the second frontside power rail, and wherein the second transistor is configured to receive the second supply voltage from the first backside power rail and the second backside power rail.

3 . The integrated circuit of claim 2 ,
wherein the first transistor is in a first active region of the integrated circuit and extends in the first direction, wherein the second transistor is disposed in a second active region of the integrated circuit and extends in the first direction, and wherein the first active region does not overlap the first frontside power rail and the second frontside power rail, and the second active region does not overlap the first backside power rail and the second backside power rail.

4 . The integrated circuit of claim 2 ,
wherein the first frontside power rail and the first backside power rail at least partially overlap each other in the vertical direction, and wherein the second frontside power rail and the second backside power rail at least partially overlap each other in the vertical direction.

5 . The integrated circuit of claim 1 ,
wherein the at least one backside power rail comprises a first backside power rail below the complementary field effect transistor in the vertical direction and extending in a first direction, wherein the at least one frontside power rail comprises a first frontside power rail above the complementary field effect transistor in the vertical direction and extending in the first direction, wherein the first transistor is configured to receive the first supply voltage from the first frontside power rail, and wherein the second transistor is configured to receive the second supply voltage from the first backside power rail.

6 . The integrated circuit of claim 5 ,
wherein the first transistor is in a first active region of the integrated circuit extending in the first direction, wherein the second transistor is in a second active region of the integrated circuit extending in the first direction, wherein the first active region at least partially overlaps the first backside power rail, and wherein the second active region at least partially overlaps the first frontside power rail.

7 . The integrated circuit of claim 5 , wherein the first frontside power rail and the first backside power rail do not overlap each other in the vertical direction.

8 . The integrated circuit of claim 5 , wherein the first frontside power rail and the first backside power rail at least partially overlap each other in the vertical direction.

9 . The integrated circuit of claim 1 ,
wherein the first transistor comprises a P-type transistor, and the second transistor comprises an N-type transistor, wherein the first supply voltage is a positive supply voltage, and the second supply voltage is a negative supply voltage, wherein the at least one frontside power rail is configured to transmit the positive supply voltage to a source of the P-type transistor, and wherein the at least one backside power rail is configured to transmit the negative supply voltage to a source of the N-type transistor.

10 . The integrated circuit of claim 1 ,
wherein the first transistor comprises an N-type transistor, and the second transistor comprises a P-type transistor, wherein the first supply voltage is a negative supply voltage, and the second supply voltage is a positive supply voltage, wherein the at least one frontside power rail is configured to transmit the negative supply voltage to a source of the N-type transistor, and wherein the at least one backside power rail is configured to transmit the positive supply voltage to a source of the P-type transistor.

11 . The integrated circuit of claim 1 , wherein the gate line extends in the vertical direction and is connected to the first transistor and the second transistor.

12 . The integrated circuit of claim 1 ,
wherein the first transistor is in a first active region of the integrated circuit, and the second transistor is disposed in a second active region of the integrated circuit, and wherein the gate line surrounds the first active region and the second active region.

13 . The integrated circuit of claim 12 , further comprising a first contact on the first active region,
wherein the via structure connects the second transistor to the first contact.

14 . An integrated circuit comprising:
a first active region and a second active region arranged, in a vertical direction with respect to a substrate, on a front side of the substrate; a gate line extending in the vertical direction and connected to the first active region and the second active region; a via structure extending in the vertical direction on the second active region and connecting the first active region to the second active region; a frontside power rail above the first active region in the vertical direction and configured to transmit a first supply voltage to the first active region; a backside power rail on a back side of the substrate and configured to transmit a second supply voltage to a source/drain region of the second active region; and a direct backside contact extending in the vertical direction on the backside power rail and connecting the backside power rail to the source/drain region of the second active region, wherein the first supply voltage and the second supply voltage are different.

15 . The integrated circuit of claim 14 ,
wherein the first supply voltage is a positive supply voltage, and the second supply voltage is a negative supply voltage, wherein the frontside power rail is configured to transmit the positive supply voltage to a source/drain region of the first active region, and wherein the backside power rail is configured to transmit the negative supply voltage to the source/drain region of the second active region.

16 . The integrated circuit of claim 14 ,
wherein the first supply voltage is a negative supply voltage, and the second supply voltage is a positive supply voltage, wherein the frontside power rail is configured to tr

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jaeha
• Kim Sukjin
• Park Sangdo
• Lee Yongho
• Choi Hongmook

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/427 Primary

  Power or ground buses · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/856 Primary

  the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS · CPC title

• H10D88/01

  Manufacture or treatment · CPC title