Secure Exclaves

US2025094565A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2025094565-A1
Application numberUS-202418790895-A
CountryUS
Kind codeA1
Filing dateJul 31, 2024
Priority dateSep 20, 2023
Publication dateMar 20, 2025
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Techniques are disclosed relating to securing hardware accelerators used by a computing device. In some embodiments, a computing device includes user interface and user interface pipeline circuitry coupled to the user interface. The user interface pipeline circuitry is configured to process a set of data received from a first source to produce an output for the user interface of the computing device, receive, from a second source, an indication that a component of the computing device has been activated, and, prior to presenting the output via the user interface, insert, into the output, an indicator of the component being activated.

First claim

Opening claim text (preview).

What is claimed is: 1 . A computing device, comprising: user interface; and user interface pipeline circuitry coupled to the user interface and configured to: process a set of data received from a first source to produce an output for the user interface of the computing device; receive, from a second source, an indication that a component of the computing device has been activated; and prior to presenting the output via the user interface, insert, into the output, an indicator of the component being activated. 2 . The computing device of claim 1 , wherein the component is a sensor configured to collect sensitive data about a user. 3 . The computing device of claim 1 , wherein the component is a camera configured to collect image data. 4 . The computing device of claim 1 , wherein the component is a microphone configure to capture audio data. 5 . The computing device of claim 1 , wherein the user interface is a display, and wherein the user interface pipeline circuitry is display pipeline circuitry configured to: produce frames for the display of the computing device, wherein the display pipeline circuitry includes a blend pipeline stage configured to: based on the received indication, insert pixel data as the indicator into a frame being rendered by the display pipeline circuitry. 6 . The computing device of claim 1 , wherein the user interface is a speaker, and wherein the user interface pipeline circuitry is an audio pipeline circuitry configured to: produce an audio signal for the speaker of the computing device, wherein the audio pipeline circuitry includes a blend pipeline stage configured to: based on the received indication, insert an audio indicator into the audio signal. 7 . The computing device of claim 1 , wherein the user interface is a haptic feedback engine, and wherein the user interface pipeline circuitry is haptic pipeline circuitry configured to: produce a haptic feedback data for a haptic feedback engine, wherein the haptic pipeline circuitry includes a blend pipeline stage configured to: based on the received indication, insert a particular haptic indicator into the haptic feedback data. 8 . The computing device of claim 1 , further comprising: one or more processors; and memory having program instructions stored therein that are executable by the one or processors to: provide, via a first untrusted process corresponding to the first source, the set of data to the user interface pipeline circuitry; and provide, via a second trusted process corresponding to the second source, the indication to the user interface pipeline circuitry. 9 . The computing device of claim 1 , wherein the user interface pipeline circuitry includes: a first direct memory access (DMA) engine configured to retrieve the set of data from a memory; and a second, different DMA engine configured to retrieve the indication from the memory. 10 . The computing device of claim 1 , wherein the user interface pipeline circuitry includes an extraction stage configured to: extract data corresponding to where the indicator is inserted into the output to confirm that the indicator remains inserted into the output prior to the output being presented via the user interface. 11 . The computing device of claim 10 , further comprising: one or more processors; and memory having program instructions stored therein that are executable by the one or processors to: receive the extracted data corresponding to where the indicator is inserted into the output; and analyze the received extracted data to determine whether the indicator remains inserted into the output. 12 . The computing device of claim 10 , further comprising: sensor pipeline circuitry configured to: process data received from the activated component; and in response the indicator remaining inserted into the output, provide the processed data to a destination. 13 . The computing device of claim 12 , wherein the sensor pipeline circuitry includes: a dead man's switch configured to: periodically receiving confirmation that the indicator remains inserted into the output; and in response to an omission of the confirmation, interrupting providing the processed data to the destination. 14 . The computing device of claim 12 , wherein the sensor pipeline circuitry implements an image sensor pipeline configured to process images received from a camera. 15 . The computing device of claim 12 , wherein the sensor pipeline circuitry implements an audio sensor pipeline configured to process an audio signal received from a microphone. 16 . A computing device, comprising: a user interface; and user interface pipeline circuitry coupled to the user interface and configured to: process a set of data to produce an output for the user interface of the computing device; extract, from the output prior to presenting the output via the user interface, data corresponding to where an indicator is inserted into the output to indicate that a component of the computing device has been activated; and provide the extracted data for analysis to determine whether the indicator remains inserted into the output. 17 . The computing device of claim 16 , further comprising: one or more processors; and memory having program instructions stored therein that are executable by the one or processors to: determine, from the provided extracted data, whether the indicator remains inserted into the output; and in response to determining that the indicator does not remain inserted into the output, cause interruption of a task associated with the indicator. 18 . The computing device of claim 16 , further comprising: a sensor; and sensor pipeline circuitry configured to: process data received from the sensor; and in response the indicator remaining inserted into the output, provide the processed data to a destination. 19 . The computing device of claim 16 , wherein the user interface pipeline circuitry includes: a first direct memory access (DMA) engine configured to retrieve the set of data for processing; and a second, different DMA engine configured to provide the extracted data to a destination for analysis. 20 . A method, comprising: processing, by user interface pipeline circuitry of a computing device, a set of data received from a source to produce an output for a user interface of the computing device; prior to presenting the output via the user interface: inserting, by a first stage of the user interface pipeline circuitry into the output, an indicator of a component being activated; and extracting, by a second stage of the user interface pipeline circuitry from the output, data corresponding to where the indicator is inserted to confirm that indicator remains inserted.

Assignees

Inventors

Classifications

  • operating in dual or compartmented mode, i.e. at least one secure mode · CPC title

  • G06F21/53Primary

    by executing in a restricted environment, e.g. sandbox or secure virtual machine · CPC title

  • to a system of files or objects, e.g. local or distributed file system or database · CPC title

  • by adding security routines or objects to programs · CPC title

  • Test or assess software · CPC title

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Frequently asked questions

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What does patent US2025094565A1 cover?
Techniques are disclosed relating to securing hardware accelerators used by a computing device. In some embodiments, a computing device includes user interface and user interface pipeline circuitry coupled to the user interface. The user interface pipeline circuitry is configured to process a set of data received from a first source to produce an output for the user interface of the computing d…
Who is the assignee on this patent?
Apple Inc
What technology area does this patent fall under?
Primary CPC classification G06F21/53. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Mar 20 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).