Super system on chip

Patent metadata

Field	Value
Publication number	US-2025094380-A1
Application number	US-202418831207-A
Country	US
Kind code	A1
Filing date	Sep 14, 2024
Priority date	Sep 28, 2019
Publication date	Mar 20, 2025
Grant date	—

Abstract

A Super System is disclosed and its inputs/outputs are coupled with a Mach-Zehnder interferometer (MZI), wherein the Mach-Zehnder interferometer (MZI) can be coupled with a first optical waveguide either in a two-dimensional (2-D) or in a three-dimensional (3-D) arrangement. The first optical waveguide can be then coupled with (i) a semiconductor optical amplifier (SOA) and/or (ii) a second optical waveguide (that can include an optical resonator) either in a two-dimensional (2-D) or in a three-dimensional (3-D) arrangement. The Super System can include multipliers of matrices and graphic processors.

First claim

I claim:

1 . A Super System,
wherein the Super System is a Super System on Chip (SSoC) or a Super System on Package (SSoP), wherein the Super System comprises:
(a) an input of the Super System or an output of the Super System;
wherein the input of the Super System or the output of the Super System is coupled with a Mach-Zehnder interferometer (MZI),
wherein the Mach-Zehnder interferometer (MZI) is coupled with a first optical waveguide in a three-dimensional (3-D) arrangement,
wherein the first optical waveguide is coupled with (i) a semiconductor optical amplifier (SOA) in the three-dimensional (3-D) arrangement and/or (ii) a second optical waveguide in the three-dimensional (3-D) arrangement,
wherein the second optical waveguide includes an optical resonator,

(b) one or more third optical waveguides; and
wherein at least one of the one or more third optical waveguides is coupled with the Super System,
wherein at least one of the one or more third optical waveguides comprises a nonlinear optical material,

(c) (i) one or more multipliers of matrices and/or (ii) graphic processors,
wherein the graphic processors are stacked in the three-dimensional (3-D) arrangement.

2 . The Super System according to claim 1 , wherein the Super System is coupled with an electronic component selected from the group consisting of a processor-specific electronic integrated circuit (Processor-EIC), an application specific integrated circuit (ASIC) and a field programmable gate array (FPGA).

3 . The Super System according to claim 2 , wherein the processor-specific electronic integrated circuit (Processor-EIC) comprises (i) a vertically stacked structure or (ii) a three-dimensionally (3-D) stacked structure or (iii) stacked dual layers of ultra-thin film of hexagonal boron nitride.

4 . The Super System according to claim 2 , wherein the processor-specific electronic integrated circuit (Processor-EIC) comprises a gate oxide that includes zirconium oxide and/or hafnium oxide.

5 . The Super System according to claim 2 , wherein the processor-specific electronic integrated circuit (Processor-EIC) comprises a material selected from consisting of silicon, germanium, a silicon-germanium (SiGe) composition, a silicon-germanium (SiGe) superlattice, an indium gallium zinc oxide composition, a III-V material, a two-dimensional material, a one-dimensional material and a superatomic material.

6 . The Super System according to claim 2 , wherein the processor-specific electronic integrated circuit (Processor-EIC) comprises a multi-part gate and a memory element, wherein the memory element includes one or more memory circuits.

7 . The Super System according to claim 2 , wherein the processor-specific electronic integrated circuit (Processor-EIC) comprises one or more processing cores and one or more memory units, wherein at least one of the one or more processing cores and at least one of the one or more memory units are intertwined either in a two-dimensional (2-D) arrangement or in a three-dimensional (3-D) arrangement, wherein at least one of the one or more memory units includes one or more memory elements, wherein at least one of the one or more memory elements includes one or more memory circuits.

8 . The Super System according to claim 2 , wherein the processor-specific electronic integrated circuit (Processor-EIC) comprises a cross-bar array, wherein the cross-bar array includes a ferroelectric semiconductor.

9 . The Super System according to claim 1 , wherein the Super System is further coupled with an optical switch or an optical interface, wherein the optical interface comprises light sources and photodiodes.

10 . The Super System according to claim 1 , is a part of a multichip module (MCM), wherein the multichip module (MCM) comprises an array of light sources, an array of photodiodes and an array of lenses.

11 . The Super System according to claim 1 , is further communicatively interfaced with a set of computer implementable instructions in artificial neural networks (ANN), wherein the set of computer implementable instructions is stored in one or more non-transitory storage media.

12 . The Super System according to claim 11 , wherein the set of computer implementable instructions in the artificial neural networks (ANN) comprises a transformer model based computer implementable instructions or a diffusion model based computer implementable instructions.

13 . The Super System according to claim 11 , wherein the set of computer implementable instructions in the artificial neural networks (ANN) comprises Kolmogorov-Arnold based neural network architecture (KANN) or Poisson flow generative model++ (PFGM++).

14 . The Super System according to claim 11 , wherein the set of computer implementable instructions in the artificial neural networks (ANN) comprises an evolutionary algorithm based computer implementable instructions and/or a game theory based computer implementable instructions.

15 . The Super System according to claim 1 , is further communicatively interfaced with a set of computer implementable instructions in computer vision or Vision Transformer (ViT), wherein the set of computer implementable instructions is stored in one or more non-transitory storage media.

16 . The Super System according to claim 1 , is further communicatively interfaced with a set of computer implementable instructions in self-learning based on a text, an image, a video and an experience, wherein the set of computer implementable instructions is stored in one or more non-transitory storage media.

17 . A Super System,
wherein the Super System is a Super System on Chip (SSoC) or a Super System on Package (SSoP), wherein the Super System comprises:
(a) an input of the Super System or an output of the Super System;
wherein the input of the Super System or the output of the Super System is coupled with a Mach-Zehnder interferometer (First MZI),
wherein the Mach-Zehnder interferometer (MZI) comprises a material selected from the group consisting of a phase transition material, a phase change material,
a lithium niobate material and a polymeric material,
wherein the phase transition material is electrically and/or optically controlled,
wherein the phase change material is electrically or optically controlled,
wherein the lithium niobate material is electrically controlled,
wherein the polymeric material is electrically controlled,
wherein the Mach-Zehnder interferometer (MZI) is coupled with a first optical waveguide in a three-dimensional (3-D) arrangement,
wherein the first optical waveguide is coupled with (i) a semiconductor optical amplifier (SOA) or a first optical resonator in the three-dimensional (3-D) arrangement and/or (ii) a second optical waveguide in the three-dimensional (3-D) arrangement,
wherein the second optical waveguide comprises a second optical resonator,
wherein the second optical resonator includes a nonlinear optical material,

(b) one or more third optical waveguides; and
wherein at least one of the one or more third optical waveguides is coupled with either the input of the Super System or the output of the Super System,

(c) one or more (i) multipliers of matrices and/or (ii) graphic processors.

18 . The Super System according to claim 17 , wherein the Super System is coupled with an electronic component selected from the group consisting of a processor-specific electronic integrated circuit (Processor-EIC), an application specific integrated circuit (ASIC) and a field programmab

Assignees

• Mazed Mohammad A

Inventors

• Mazed Mohammad A

Classifications

• G06F15/7807

  System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package · CPC title

• G01S7/4917

  superposing optical signals in a photodetector, e.g. optical heterodyne detection · CPC title

• G02F2203/70

  Semiconductor optical amplifier [SOA] used in a device covered by G02F · CPC title

• G02F1/365

  in an optical waveguide structure (G02F1/377, {G02F1/395} take precedence) · CPC title

• H04W12/06

  Authentication · CPC title