Memory system and method of controlling nonvolatile memory

Patent metadata

Field	Value
Publication number	US-2025094336-A1
Application number	US-202418780618-A
Country	US
Kind code	A1
Filing date	Jul 23, 2024
Priority date	Sep 14, 2023
Publication date	Mar 20, 2025
Grant date	—

Abstract

According to an embodiment, a memory system includes a nonvolatile memory including memory cells and a memory controller coupled to the nonvolatile memory. Each of the plurality of memory cells is configured to store, in a nonvolatile manner, a plurality of bits of data. The memory controller is configured to, in a case where a first memory cell stores valid first bit data as a first bit and does not store data as a second bit, and a second memory cell stores valid second bit data as the first bit and does not store data as the second bit, and upon reception of a flush command from a host, read the second bit data from the second memory cell and write the second bit data read from the second memory cell to the first memory cell as the second bit.

First claim

What is claimed is:

1 . A memory system comprising:
a nonvolatile memory including a plurality of memory cells, each of the plurality of memory cells being configured to store, in a nonvolatile manner, a plurality of bits of data including at least a first bit and a second bit, the plurality of memory cells including at least a first memory cell and a second memory cell different from the first memory cell; and a memory controller electrically coupled to the nonvolatile memory and configured to: in a case where the first memory cell stores valid first bit data as the first bit and does not store data as the second bit, and the second memory cell stores valid second bit data as the first bit and does not store data as the second bit, and upon reception of a flush command from a host,
read the second bit data from the second memory cell; and
write the second bit data read from the second memory cell to the first memory cell as the second bit.

2 . The memory system according to claim 1 , wherein
the nonvolatile memory includes a plurality of memory areas, and at least one of the plurality of memory cells included in one of the plurality of memory areas of the nonvolatile memory to which the first memory cell and the second memory cell belong does not store data as the second bit.

3 . The memory system according to claim 1 , wherein
the memory controller is further configured to: write the second bit data to the second memory cell as the first bit after writing the first bit data to the first memory cell as the first bit; and upon the reception of the flush command from the host,
read the second bit data from the second memory cell; and
write the second bit data read from the second memory cell to the first memory cell as the second bit.

4 . The memory system according to claim 1 , wherein
the nonvolatile memory includes a plurality of cell units, each of the plurality of cell units includes one or more of the plurality of memory cells, and the plurality of cell units include at least a first cell unit including the first memory cell and a second cell unit including the second memory cell, and the memory controller is further configured to: read valid data that is stored as the first bit in each of the one or more memory cells of the second cell unit including at least the second memory cell; and upon a total amount of the valid data that are read from each of the one or more memory cells of the second cell unit after the reception of the flush command from the host having reached an amount of data that allows a write operation to be performed for the first cell unit, write the second bit data read from the second memory cell as the first bit to the first memory cell.

5 . The memory system according to claim 4 , wherein
the memory controller is further configured to, in a case where the total amount of the valid data that are stored as the first bit in each of the one or more memory cells of the second cell unit at a point of time of the reception of the flush command from the host is less than the amount of data that allows the write operation to be performed for the first cell unit, write padding data to at least one of the memory cells of the first cell unit.

6 . The memory system according to claim 4 , wherein
the nonvolatile memory further includes: a first word line coupled to each of the plurality of memory cells included in the first cell unit; a second word line coupled to each of the plurality of memory cells included in the second cell unit, the second word line being different from the first word line; one or more first bit lines electrically coupled to the one or more of the plurality of memory cells included in the first cell unit; and one or more second bit lines electrically coupled to the one or more of the plurality of memory cells included in the second cell unit, the one or more second bit lines being different from the one or more first bit lines.

7 . The memory system according to claim 1 , further comprising:
a buffer, wherein the nonvolatile memory includes a plurality of cell units, each of the plurality of cell units includes one or more of the plurality of memory cells, and the plurality of cell units include at least a first cell unit including the first memory cell, and a second cell unit including the second memory cell, the memory controller is further configured to: cause the buffer to store data read from the second cell unit, the data including at least the second bit data; and upon an amount of the data stored in the buffer having reached an amount of data that allows a write operation to be performed for the first cell unit, write the second bit data stored in the buffer to the first memory cell.

8 . The memory system according to claim 7 , wherein
the memory controller is further configured to, in a case where the amount of the data stored in the buffer does not reach the amount of data that allows the write operation to be performed for the first cell unit, store padding data in the buffer and execute the write operation for the first cell unit, using the data stored in the buffer and the padding data stored in the buffer.

9 . The memory cell according to claim 7 , wherein
the memory controller is further configured to: read data from each of the one or more of the plurality of memory cells included in the second cell unit; store valid data read from the second cell unit to the buffer; and skip storing invalid data read from the second cell unit to the buffer.

10 . The memory system according to claim 1 , wherein
the plurality of memory cells further include a third memory cell and a fourth memory cell, and the memory controller is further configured to: write valid third bit data as the first bit to the third memory cell, after writing the first bit data to the first memory cell; write valid fourth bit data as the first bit to the fourth memory cell, after writing the third bit data to the third memory cell; write the second bit data to the second memory cell as the first bit, after writing the fourth bit data to the fourth memory cell; and in a case where the first memory cell stores the first bit data as the first bit and does not store data as the second bit, the second memory cell stores the second bit data as the first bit and does not store data as the second bit, the third memory cell stores the third bit data as the first bit and does not store data as the second bit, and the fourth memory cell stores the fourth bit data as the first bit and does not store data as the second bit, and upon the reception of the flush command from the host,
read the second bit data from the second memory cell;
read the fourth bit data from the fourth memory cell, after writing the second bit data read from the second memory cell to the first memory cell as the second bit; and
write the fourth bit data read from the fourth memory cell to the third memory cell as the second bit.

11 . The memory system according to claim 1 , wherein
the plurality of memory cells further include a third memory cell and a fourth memory cell, and the memory controller is further configured to: write valid third bit data as the first bit to the third memory cell, after writing the first bit data to the first memory cell; write valid fourth bit data as the first bit to the fourth memory cell, after writing the third bit data to the third memory cell; write the second bit data to the second memory cell as the first bit, after writing the fourth bit data to the fourth memory cell; and in a case where the first memory cell stores the first bit data as the first bit and does not store data as the second b

Assignees

• Kioxia Corp

Inventors

• Nishikawa Suguru
• Amaki Takehiko
• Igahara Shunichi
• Hida Toshikatsu
• Kojima Yoshihisa

Classifications

• G11C2211/5641

  Multilevel memory having cells with different number of storage levels · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/56

  using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency · CPC title