Memory apparatus, test fixture, and test system

Patent metadata

Field	Value
Publication number	US-2025094301-A1
Application number	US-202418441746-A
Country	US
Kind code	A1
Filing date	Feb 14, 2024
Priority date	Sep 18, 2023
Publication date	Mar 20, 2025
Grant date	—

Abstract

Examples of the present disclosure provide a memory apparatus, a test fixture, and a test system. The memory apparatus includes a main circuit board and a memory controller. The main circuit board includes a test interface configured to receive first startup data. The memory controller is disposed on the main circuit board and connected to the test interface, and second startup data is stored in the memory controller. The memory controller is configured to acquire the second startup data, in response to determining that acquiring the second startup data fails, acquire the first startup data through the test interface, and perform an initialization operation on the memory apparatus according to the first startup data.

First claim

What is claimed is:

1 . A memory apparatus, comprising:
a main circuit board comprising a test interface configured to receive first startup data; and a memory controller disposed on the main circuit board and connected to the test interface, wherein the memory controller stores second startup data, and the memory controller is configured to:
acquire the second startup data;
in response to determining that acquiring the second startup data fails, acquire the first startup data through the test interface; and
perform an initialization operation on the memory apparatus according to the first startup data.

2 . The memory apparatus of claim 1 , wherein the memory controller is configured to:
in response to determining that acquring the second startup data fails, enable, based on a select signal, an external storage device that provides the first startup data, generate a startup data request signal, and receive the first startup data provided by the external storage device in response to the startup data request signal; and wherein the test interface is further configured to output the select signal and the startup data request signal.

3 . The memory apparatus of claim 2 , wherein the memory controller is configured to:
output a clock signal through the test interface and sample the first startup data based on the clock signal; and provide a supply voltage and a ground voltage to the external storage device through the test interface.

4 . The memory apparatus of claim 3 , wherein the test interface comprises a plurality of test pads; and
the memory controller is connected with the plurality of test pads, so as to output the select signal, the startup data request signal, the clock signal, the supply voltage, and the ground voltage, and receive the first startup data through the plurality of test pads.

5 . The memory apparatus of claim 4 , wherein the test interface comprises:
a first test pad connected to a supply pin of the memory controller and configured to output the supply voltage; a second test pad connected to a ground pin of the memory controller and configured to output the ground voltage; a third test pad connected to a chip select signal pin of the memory controller and configured to output the select signal; a fourth test pad connected to a clock pin of the memory controller and configured to output the clock signal; a fifth test pad connected to a signal output pin of the memory controller and configured to output the startup data request signal; and a sixth test pad connected to a signal input pin of the memory controller and configured to receive the first startup data.

6 . The memory apparatus of claim 1 , wherein the first startup data comprises a read-only memory code and a bootloader; and
the memory controller is configured to: run a read-only memory program according to the read-only memory code, verify the bootloader using the read-only memory program, and run the bootloader according to the verified bootloader, so as to complete the initialization operation.

7 . The memory apparatus of claim 1 , wherein the memory controller is further configured to:
after being powered on, acquire the second startup data; and when succeeding in acquiring the second startup data, perform the initialization operation on the memory apparatus according to the second startup data.

8 . The memory apparatus of claim 1 , wherein the main circuit board comprises a first side and a second side disposed oppositely, the memory controller is disposed on the first side of the main circuit board, and the test interface is disposed on the first side or the second side of the main circuit board.

9 . The memory apparatus of claim 8 , further comprising: an input/output connector disposed at an end of the main circuit board, wherein the test interface is located between the memory controller and the input/output connector; and
wherein the memory apparatus further comprises:
a non-volatile memory disposed on the first side of the main circuit board and located on a side of the memory controller away from the input/output connector.

10 . The memory apparatus of claim 9 , wherein the memory controller is configured to:
when failing to acquire the second startup data, output a startup data load failure signal through the input/output connector.

11 . A test fixture, comprising:
a test substrate; a startup data storage device disposed on the test substrate, wherein first startup data is stored in the startup data storage device; and a test connector disposed on the test substrate and connected with the startup data storage device, wherein the test connector is configured for contact connection with a test interface on a memory apparatus.

12 . The test fixture of claim 11 , wherein the startup data storage device comprises: a read-only memory, wherein the first startup data is stored in the read-only memory.

13 . The test fixture of claim 11 , wherein the test connector comprises: a plurality of ejector pins each being configured for contact connection with one test pad in the test interface.

14 . The test fixture of claim 11 , further comprising:
a signal conversion module disposed on the test substrate; a first conversion interface connected with the signal conversion module; and a second conversion interface connected with the signal conversion module and configured to connect with an input/output connector of the memory apparatus, wherein the second conversion interface is different from the first conversion interface.

15 . The test fixture of claim 14 , wherein a switch is disposed between the test connector and the startup data storage device; and
after the memory apparatus outputs a startup data load failure signal, the switch is closed to enable the startup data storage device.

16 . A test system, comprising:
a test fixture comprising: a startup data storage device and a test connector disposed on a test substrate, wherein first startup data is stored in the startup data storage device, and the test connector is connected with the startup data storage device; and a memory apparatus comprising: a main circuit board and a memory controller, wherein the main circuit board comprises a test interface, the memory controller is disposed on the main circuit board and connected with the test interface, the memory apparatus is installed on the test fixture, and the test interface and the test connector are in contact connection.

17 . The test system of claim 16 , wherein the memory controller stores second startup data; and
the memory controller is configured to: acquire the second startup data; when failing to acquire the second startup data, acquire first startup data in the startup data storage device; and perform an initialization operation on the memory apparatus according to the first startup data.

18 . The test system of claim 17 , wherein the memory controller is configured to:
when failing to acquire the second startup data, enable the startup data storage device based on a select signal, send a startup data request signal to the startup data storage device, and receive the first startup data provided by the startup data storage device in response to the startup data request signal.

19 . The test system of claim 18 , wherein the test interface comprises a plurality of test pads, and the memory controller is connected with the plurality of test pads; and
the test connector comprises a plurality of ejector pins, the startup data storage device is connected with the

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Zhu Jie

Classifications

• G06F11/1458

  Management of the backup or restore process · CPC title

• G06F11/1417

  Boot up procedures · CPC title

• G06F11/2733 Primary

  Test interface between tester and unit under test · CPC title