Display substrate, maintenance method and display device

US2025089365A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2025089365-A1
Application numberUS-202218557810-A
CountryUS
Kind codeA1
Filing dateJul 28, 2022
Priority dateJul 28, 2022
Publication dateMar 13, 2025
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display substrate including a base substrate and a driving module arranged on the base substrate, the driving module includes at least one driving unit, and the driving unit includes N stages of driving circuits; N is a positive integer, n is a positive integer less than or equal to N; the nth stage of driving circuit includes a (2n−1)th stage of output circuit, a 2nth stage of output circuit and a first node control circuit; the first node is electrically connected to the (2n−1)th stage of output circuit and the 2nth stage of output circuit respectively through a first connection line; the driving module also includes a scanning line; there are at least two mutually independent overlapping portions between the orthographic projection of the first connection line on the base substrate and the orthographic projection of the scanning line on the base substrate.

First claim

Opening claim text (preview).

1 . A display substrate, comprising a base substrate and a driving module arranged on the base substrate, wherein the driving module includes at least one driving unit, and the driving unit includes N stages of driving circuits; N is a positive integer, n is a positive integer less than or equal to N; an nth stage of driving circuit includes a (2n−1)th stage of output circuit, a 2nth stage of output circuit and a first node control circuit; the first node control circuit is electrically connected to a first node and is configured to control a potential of the first node; the (2n−1)th stage of output circuit is electrically connected to the first node and a (2n−1)th stage of driving output terminal, and is configured to control the (2n−1)th stage of driving output terminal to provide a (2n−1)th stage of scanning signal under the control of the potential of the first node; the 2nth stage of output circuit is electrically connected to the first node and a 2nth stage of driving output terminal respectively, and is configured to control the 2nth stage of driving output terminal to provide a 2nd stage of scanning signal under the control of the potential of the first node; the first node is electrically connected to the (2n−1)th stage of output circuit and the 2nth stage of output circuit respectively through a first connection line; the driving module further includes a scanning line; there are at least two mutually independent overlapping portions between an orthographic projection of the first connection line on the base substrate and an orthographic projection of the scanning line on the base substrate. 2 . The display substrate according to claim 1 , wherein the nth stage of driving circuit further includes a second node control circuit; the second node control circuit is electrically connected to a second node and is configured to control a potential of the second node; the (2n−1)th stage of output circuit is also electrically connected to the second node, and is also configured to control the (2n−1)th stage of driving output terminal to provide the (2n−1)th stage of scanning signal under the control of the potential of the second node; the 2nth stage of output circuit is also electrically connected to the second node, and is further configured to control the 2nth stage of driving output terminal to provide the 2nth stage of scanning signal under the control of the potential of the second node; the second node is electrically connected to the (2n−1)th stage of output circuit and the 2nth stage of output circuit through a second connection line; there are at least two mutually independent overlapping portions between an orthographic projection of the second connection line on the base substrate and the orthographic projection of the scanning line on the base substrate. 3 . The display substrate according to claim 1 , wherein the first connection line includes a first connection line part, a first conducting line, a second conducting line and a second connection line part; the first node is electrically connected to the (2n−1)th stage of output circuit through the first connection line part, and the first connection line part is respectively electrically connected to the first conducting line and the second conducting line, and the first conducting line and the second conducting line are electrically connected to the 2nth stage of driving circuit through the second connection line part respectively; there is a first overlapping portion between the orthographic projection of the scanning line on the base substrate and an orthographic projection of the first conducting line on the base substrate, there is a second overlapping portion between the orthographic projection of the scanning line on the base substrate and an orthographic projection of the second conducting line on the base substrate; the first overlapping portion and the second overlapping portion are independent of each other, wherein a line width of the first conducting line is greater than or equal to 5 um and less than or equal to 10 um, and a line width of the second conducting line is greater than or equal to 5 um and less than or equal to 10 um; a distance between the first conducting line and the second conducting line is greater than or equal to 6 um and less than or equal to 8 um. 4 . (canceled) 5 . The display substrate according to claim 2 , wherein the second connection line includes a third connection line part, a third conducting line, a fourth conducting line and a fourth connection line part; the second node is electrically connected to the 2nth stage of output circuit through the third connection line part, and the third connection line part is respectively electrically connected to the third conducting line and the fourth conducting line, and the third conducting line and the fourth conducting line are respectively electrically connected to the (2n−1)th stage of driving circuit through the fourth connection line part; there is a third overlapping portion between the orthographic projection of the scanning line on the base substrate and an orthographic projection of the third conducting line on the base substrate, there is a fourth overlapping portion between the orthographic projection of the scanning line on the base substrate and an orthographic projection of the fourth conducting line on the base substrate; the third overlapping portion and the fourth overlapping portion are independent of each other, wherein a line width of the third conducting line is greater than or equal to Sum and less than or equal to 10 um, and a line width of the fourth conducting line is greater than or equal to 5 um and less than or equal to 10 um; a distance between the third conducting line and the fourth conducting line is greater than or equal to 6 um and less than or equal to 8 um. 6 . (canceled) 7 . The display substrate according to claim 1 , wherein the scanning line includes a first scanning connection line, a first scanning line part, a second scanning line part, and a second scanning connection line; the first scanning connection line is electrically connected to the second scanning connection line through the first scanning line part and the second scanning line part; there is a fifth overlapping portion between the orthographic projection of the first connection line on the base substrate and an orthographic projection of the first scanning line part on the base substrate, there is a sixth overlapping portion between the orthographic projection of the first connection line on the base substrate and an orthographic projection of the second scanning line part on the base substrate; the fifth overlapping portion and the sixth overlapping portion are independent of each other, wherein a line width of the first scanning line part is greater than or equal to 5 um and less than or equal to 10 um, and a line width of the second scanning line part is greater than or equal to 5 um and less than or equal to 10 um, a distance between the first scanning line part and the second scanning line part is greater than or equal to 6 um and less than or equal to 8 um. 8 . (canceled) 9 . The display substrate according to claim 2 , wherein the scanning line include a third scanning connection line, a third scanning line part, a fourth scanning line part and a fourth scanning connection line; the third scanning connection line is electrically connected to the fourth scanning connection line through the third scanning line part and the fourth scanning line part, and there is a seventh overlapping portion between the orthographic projection of the second connection line on the base substrate and an orthographic projection of the third scanning line part on the base substrat

Assignees

Inventors

Classifications

  • Testing or measuring during manufacture or treatment of wafers, substrates or devices · CPC title

  • Interconnections, e.g. scanning lines · CPC title

  • using liquid crystals · CPC title

  • for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

  • Details of drivers for scan electrodes · CPC title

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What does patent US2025089365A1 cover?
A display substrate including a base substrate and a driving module arranged on the base substrate, the driving module includes at least one driving unit, and the driving unit includes N stages of driving circuits; N is a positive integer, n is a positive integer less than or equal to N; the nth stage of driving circuit includes a (2n−1)th stage of output circuit, a 2nth stage of output circuit…
Who is the assignee on this patent?
Hefei Boe Joint Tech Co Ltd, Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/006. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Mar 13 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).