Hybrid addressing for imaging and vision data

US2025088770A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2025088770-A1
Application numberUS-202418960448-A
CountryUS
Kind codeA1
Filing dateNov 26, 2024
Priority dateJul 22, 2022
Publication dateMar 13, 2025
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In an example, a method includes receiving image data of an input image having lines therein. The method also includes storing a first portion of the image data in a circular buffer in a first memory, wherein the first portion begins at a circular buffer start line in the input image and ends at a circular buffer end line in the input image. The method includes storing a second portion of the image data in a linear buffer in a second memory, where the second portion is non-overlapping with the first portion. The method includes processing the second portion of the image data to produce a first block of an output image. The method includes processing the first portion of the image data to produce a second block of the output image.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method, comprising: receiving data corresponding to a set of lines of an image; determining a first line and a second line out of the set of lines, which correspond to a first portion of the image; determining a third line out of the set of lines, which corresponds to a second portion of the image; storing a first subset of the data, identified based on the first line and the second line, in a first buffer; and storing a second subset of the data, identified based on at least the third line, in a second buffer, wherein the second buffer is a different type of buffer from the first buffer. 2 . The method of claim 1 , wherein the first portion corresponds to a center portion of the image. 3 . The method of claim 1 , wherein the second portion corresponds to an edge portion of the image. 4 . The method of claim 1 , wherein the first buffer is a circular buffer. 5 . The method of claim 1 , wherein the second buffer is a linear buffer. 6 . The method of claim 1 , wherein the first buffer is part of on-chip memory. 7 . The method of claim 1 , wherein the second buffer is part of off-chip memory. 8 . The method of claim 1 , further comprising: obtaining the first subset of the data from the first buffer to render the first portion of the image; and obtaining the second subset of the data from the second buffer to render the second portion the image. 9 . The method of claim 8 , wherein obtaining the second subset of the data from the second buffer is performed prior to obtaining the first subset of the data from the first buffer. 10 . The method of claim 1 , further determining the first line and the second line comprises determining the first line and the second line based on a size of the first buffer. 11 . A system, comprising: a first buffer; a second buffer that is a different type of buffer from the first buffer; and processing circuitry configured to: receive data corresponding to a set of lines of an image; determine a first line and a second line out of the set of lines, which correspond to a first portion of the image; determine a third line out of the set of lines, which corresponds to a second portion of the image; store a first subset of the data, identified based on the first line and the second line, in the first buffer; and store a second subset of the data, identified based on at least the third line, in the second buffer. 12 . The system of claim 11 , wherein the first portion corresponds to a center portion of the image. 13 . The system of claim 11 , wherein the second portion corresponds to an edge portion of the image. 14 . The system of claim 11 , wherein the first buffer is a circular buffer. 15 . The system of claim 11 , wherein the second buffer is a linear buffer. 16 . The system of claim 11 , wherein the first buffer is part of on-chip memory. 17 . The system of claim 11 , wherein the second buffer is part of off-chip memory. 18 . The system of claim 11 , wherein the processing circuitry is further configured to: process the first subset of the data out of the first buffer to render the first portion of the image; and process the second subset of the data out of the second buffer to render the second portion of the image. 19 . The system of claim 11 , wherein the processing circuitry is further configured to: determine the first line and the second line based on a size of the first buffer. 20 . A non-transitory computer readable medium storing instructions that when executed by one or more processors cause the one or more processors to: receive data corresponding to a set of lines of an image; determine a first line and a second line out of the set of lines, which correspond to a first portion of the image; determine a third line out of the set of lines, which corresponds to a second portion of the image; store a first subset of the data, identified based on the first line and the second line, in a circular buffer; and store a second subset of the data, identified based on at least the third line, in a linear buffer.

Assignees

Inventors

Classifications

  • for suppressing or minimising disturbance in the image signal generation · CPC title

  • H04N25/77Primary

    Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

  • H04N23/698Primary

    for achieving an enlarged field of view, e.g. panoramic image capture · CPC title

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Frequently asked questions

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What does patent US2025088770A1 cover?
In an example, a method includes receiving image data of an input image having lines therein. The method also includes storing a first portion of the image data in a circular buffer in a first memory, wherein the first portion begins at a circular buffer start line in the input image and ends at a circular buffer end line in the input image. The method includes storing a second portion of the i…
Who is the assignee on this patent?
Texas Instruments Inc
What technology area does this patent fall under?
Primary CPC classification H04N25/77. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Mar 13 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).