Synchronous, full duplex daisy-chained communication system

Patent metadata

Field	Value
Publication number	US-2025088340-A1
Application number	US-202318464512-A
Country	US
Kind code	A1
Filing date	Sep 11, 2023
Priority date	Sep 11, 2023
Publication date	Mar 13, 2025
Grant date	—

Abstract

A communication system includes a plurality of nodes connected in a daisy-chain via respective bus links, wherein the plurality of nodes are configured for full duplex, synchronized communication via a carrier-based modulation scheme over the bus links. A node is configured to: transmit a downstream synchronization control header (DnSCH) to a downstream node; receive an upstream synchronization response header (UpSRH) from the downstream node; measure a delay between the DnSCH and the UpSRH; send delay information to the downstream node in a DnSCH; receive a time adjusted UpSRH; and communicate with the downstream node and any upstream node over frames based on the delay information. The frames may include a header; a flexible payload defined by a stream mapping that assigns a byte location within the flexible payload to a stream; and a footer.

First claim

1 . A node connected in a daisy-chain over full duplex links to one or more other nodes, the node configured to:
transmit a downstream synchronization control header (DnSCH) to a downstream node; receive an upstream synchronization response header (UpSRH); measure a delay between the DnSCH and the UpSRH; send delay information to the downstream node in a DnSCH; receive a time adjusted UpSRH; and communicate with the downstream node and any upstream node over frames based on the delay information.

2 . The node of claim 1 , wherein communication uses full duplex carrier-based modulation on an upstream signal and a downstream signal over the full duplex links.

3 . The node of claim 1 , wherein to communicate with the downstream node and any upstream node, the node is configured to sample data for a flexible payload at a same time as the other nodes based on the delay information.

4 . The node of claim 1 , wherein each frame includes:
a header; a flexible payload defined by a stream mapping that assigns byte locations within the flexible payload to a stream; and a footer.

5 . The node of claim 4 , wherein for a downstream frame, the header is the DnSCH and includes:
a synchronization byte with a modulo frame counter, a command field, data field, a data or address field, a general purpose input output (GPIO) over distance byte, and a cyclic redundancy check for the header; and the footer includes: cyclic redundancy check (CRC) bytes for the flexible payload and a frame valid indication with separate CRC bits.

6 . The node of claim 4 , wherein for an upstream frame, the header is the UpSRH and includes a synchronization byte, a response/request field, data field, and a cyclic redundancy check for the header, and the footer includes an interrupt request (IRQ) byte, a general purpose input output (GPIO) byte, CRC bytes for the flexible payload, and a frame valid indication with separate CRC bits.

7 . The node of claim 6 , wherein the GPIO over distance byte indicates an update to a status of virtual GPIO pins, wherein the node is configured to output virtual GPIO pin information on GPIO output pins.

8 . The node of claim 7 , wherein the node is configured to:
perform a logical operation on an uplink received status of the virtual GPIO pins and a local status of GPIO pins; forward a result of the logical operation in a GPIO over distance byte in the footer of an uplink frame; and send updated virtual GPIO information downstream from a main node to all sub nodes in a GPIO over distance byte in the header of a downstream frame.

9 . The node of claim 7 , wherein the GPIO over distance byte changes between multiple sets of virtual GPIO pins every frame to support more than 8 virtual GPIO pins.

10 . The node of claim 9 , wherein the frame valid indication with cyclic redundancy check indicates whether the frame was valid when received at a previous node.

11 . The node of claim 9 , wherein the IRQ byte indicates an interrupt request detected at a downstream node.

12 . The node of claim 11 , wherein the node is configured to select a position of the IRQ byte to indicate a local interrupt based on a priority of the local interrupt.

13 . The node of claim 9 , wherein the node is configured to generate an upstream frame including a UpSRH in an absence of a received UpSRH from the downstream node.

14 . The node of claim 4 , wherein the flexible payload includes one or more of:
an audio stream; control for a pulse width modulation duty cycle; a stream from an analog to digital converter (ADC) at a node; a serial peripheral interface (SPI) tunnel; an ethernet tunnel; or a mailbox tunnel.

15 . The node of claim 4 , wherein the flexible payload bytes are zeroes if not sourced.

16 . The node of claim 4 , wherein to communicate with the downstream node and any upstream node, the node is configured to simultaneously transmit streams at a same flexible payload locations upstream and downstream.

17 . The node of claim 4 , wherein to communicate with the downstream node and any upstream node, the node is configured apply a logical OR operation between upstream streams and downstream streams of a same position in the flexible payload.

18 . The node of claim 1 , wherein the node is configured to store a node identifier indicating a position of the node in the daisy-chain.

19 . The node of claim 1 , wherein to communicate with the downstream node and any upstream node, the node is configured to:
immediately forward information received in a downstream frame to the downstream node; immediately forward information received in an upstream frame to the upstream node; and selectively read or write data to the upstream frame or the downstream frame.

20 . A method of operating a node connected in a daisy-chain over full duplex links to one or more other nodes, comprising:
transmitting a downstream synchronization control header (DnSCH) to a downstream node; receiving an upstream synchronization response header (UpSRH); measuring a delay between the DnSCH and the UpSRH; sending delay information to the downstream node in a DnSCH; receiving a time adjusted UpSRH; and communicating with the downstream node and any upstream node over frames based on the delay information.

21 . The method of claim 20 , wherein the communicating uses full duplex carrier-based modulation on an upstream signal and a downstream signal over the full duplex links.

22 . The method of claim 20 , wherein communicating with the downstream node and any upstream node comprises sampling data for a flexible payload at a same time as the other nodes based on the delay information.

23 . The method of claim 20 , wherein each frame includes:
a header; a flexible payload defined by a stream mapping that assigns byte locations within the flexible payload to a stream; and a footer.

24 . The method of claim 23 , wherein for a downstream frame, the header is the DnSCH and includes:
a synchronization byte with a modulo frame counter, a command field, data field, a data or address field, a general purpose input output (GPIO) over distance byte, and a cyclic redundancy check for the header; and the footer includes: cyclic redundancy check (CRC) bytes for the flexible payload and a frame valid indication with separate CRC bits.

25 . The method of claim 23 , wherein for an upstream frame, the header is the UpSRH and includes a synchronization byte, a response/request field, data field, and a cyclic redundancy check for the header, and the footer includes an interrupt request (IRQ) byte, a general purpose input output (GPIO) over distance byte, CRC bytes for the flexible payload, and a frame valid indication with separate CRC bits.

26 . The method of claim 25 , wherein the GPIO over distance byte indicates an update to a status of virtual GPIO pins, the method further comprising outputting virtual GPIO pin information on GPIO output pins.

27 . The method of claim 26 , further comprising:
performing a logical operation on an uplink received status of the virtual GPIO pins and a local status of GPIO pins; forwarding a result of the logical operation in the GPIO over distance byte in the footer of an uplink frame; and including a result of the logical operation in the GPIO over distance byte to the downstream node.

28 . The method of claim 25 , where

Assignees

• Analog Devices Inc

Inventors

• Kessler Martin
• Lahr Lewis F
• Hooper William
• Puzey Matthew

Classifications

• H04L7/0033

  Correction by delay · CPC title

• H04L5/14 Primary

  Two-way operation using the same type of signal, i.e. duplex · CPC title

• H04L12/40013 Primary

  Details regarding a bus controller · CPC title