Pull-down circuit, pull-up circuit, and voltage supply circuit including pull-down circuit and pull-up circuit

Patent metadata

Field	Value
Publication number	US-2025088189-A1
Application number	US-202418809330-A
Country	US
Kind code	A1
Filing date	Aug 20, 2024
Priority date	Sep 12, 2023
Publication date	Mar 13, 2025
Grant date	—

Abstract

A pull-down circuit and a pull-up circuit for using various voltages, and a voltage supply circuit including the pull-down circuit and the pull-up circuit are disclosed. The pull-up circuit includes a sink circuit configured to receive a charge pump voltage from a charge pump circuit and pull up the charge pump voltage of the charge pump circuit to a ground voltage, wherein the charge pump voltage is less than the ground voltage, and a level shifter configured to generate a level shifter output voltage and a one-shot signal in response to a charge pump enable signal controlling the charge pump circuit wherein the level shifter output voltage controls the sink circuit, and the one-shot signal prevents floating of a node through which the level shifter output voltage is output.

First claim

What is claimed is:

1 . A pull-up circuit comprising:
a sink circuit configured to pull up an output node of a charge pump circuit to a ground voltage, wherein the charge pump circuit generates a charge pump voltage less than the ground voltage; and a level shifter configured to generate a level shifter output voltage that controls the sink circuit in response to a charge pump enable signal controlling the charge pump circuit, and to generate a one-shot signal that prevents floating of a node through which the level shifter output voltage is output.

2 . The pull-up circuit according to claim 1 , wherein the level shifter includes:
a non-overlap signal generator configured to generate a first non-overlapping signal and a second non-overlapping signal that are obtained by delaying the charge pump enable signal with different delay times.

3 . The pull-up circuit according to claim 2 , wherein the non-overlap signal generator includes:
a first path including a first NAND gate and a plurality of inverters, through which the second non-overlapping signal is output; and a second path including a second NAND gate and multiple inverters through which the first non-overlapping signal is output, wherein
the first NAND gate is configured to receive the charge pump enable signal; and
the second NAND gate is configured to receive an inverted signal of the charge pump enable signal.

4 . The pull-up circuit according to claim 2 , wherein the level shifter further includes
a voltage level controller including:
a first PMOS transistor configured to operate in response to the first non-overlapping signal; and
a first NMOS transistor configured to operate in response to the second non-overlapping signal.

5 . The pull-up circuit according to claim 4 , wherein:
the first PMOS transistor is configured to apply a power-supply voltage to a common node in response to the first non-overlapping signal of the ground voltage; and the first NMOS transistor is configured to apply the ground voltage to the common node in response to the second non-overlapping signal of the power-supply voltage.

6 . The pull-up circuit according to claim 5 , wherein the level shifter further includes:
a second PMOS transistor connected between the common node and a node through which the level shifter output voltage is output, and configured to receive the ground voltage through a gate thereof.

7 . The pull-up circuit according to claim 4 , further comprising:
a one-shot signal generator configured to generate the one-shot signal based on a gate voltage of the first PMOS transistor.

8 . The pull-up circuit according to claim 7 , wherein the one-shot signal generator includes:
a one-shot inverter configured to invert the first non-overlapping signal acting as the gate voltage of the first PMOS transistor, and to output the inverted first non-overlapping signal; and an AND gate configured to output the one-shot signal by performing an AND operation between the inverted first non-overlapping signal and the first non-overlapping signal.

9 . The pull-up circuit according to claim 1 , wherein the level shifter includes:
a second NMOS transistor connected between a node through which the level shifter output voltage is output and an output terminal of the charge pump circuit, and configured to receive the one-shot signal through a gate thereof.

10 . The pull-up circuit according to claim 1 , wherein the sink circuit includes a sink transistor, and
the level shifter includes a voltage clamping circuit connected between a gate and a source of the sink transistor, and configured to limit a voltage level to be applied to the sink transistor.

11 . A pull-down circuit comprising:
a sink circuit configured to pull down an output node of a charge pump circuit to a power-supply voltage, wherein the charge pump circuit generates a charge pump voltage greater than the power-supply voltage; and a level shifter configured to generate a level shifter output voltage that controls the sink circuit in response to a charge pump enable signal controlling the charge pump circuit, and to generate a one-shot signal that prevents floating of a node through which the level shifter output voltage is output.

12 . The pull-down circuit according to claim 11 , wherein the level shifter includes
a non-overlap signal generator configured to generate a first non-overlapping signal and a second non-overlapping signal that are obtained by delaying the charge pump enable signal with different delay times.

13 . The pull-down circuit according to claim 12 , wherein the non-overlap signal generator includes:
a first path including a first NAND gate and a plurality of inverters through which the first non-overlapping signal is output; and a second path including a second NAND gate and multiple inverters through which the second non-overlapping signal is output, wherein
the first NAND gate is configured to receive the charge pump enable signal; and
the second NAND gate is configured to receive an inverted signal of the charge pump enable signal.

14 . The pull-down circuit according to claim 12 , wherein the level shifter further includes
a voltage level controller including:
a first PMOS transistor configured to operate in response to an inverted signal of the first non-overlapping signal; and
a first NMOS transistor configured to operate in response to an inverted signal of the second non-overlapping signal.

15 . The pull-down circuit according to claim 14 , wherein:
the first PMOS transistor is configured to apply the power-supply voltage to a common node in response to the first non-overlapping signal of the power-supply voltage; and the first NMOS transistor is configured to apply a ground voltage to the common node in response to the second non-overlapping signal of the ground voltage.

16 . The pull-down circuit according to claim 15 , wherein the level shifter further includes:
a second NMOS transistor connected between the common node and a node through which the level shifter output voltage is output, and configured to receive the power-supply voltage through a gate thereof.

17 . The pull-down circuit according to claim 14 , further comprising:
a one-shot signal generator configured to generate the one-shot signal based on a gate voltage of the first NMOS transistor.

18 . The pull-down circuit according to claim 17 , wherein the one-shot signal generator includes:
a one-shot inverter configured to invert an inverted signal of the second non-overlapping signal acting as the gate voltage of the first NMOS transistor, and to output an inverted resultant signal; and an OR gate configured to output the one-shot signal by performing an OR operation between the inversion resultant signal of the inverted second non-overlapping signal and an inverted signal of the second non-overlapping signal.

19 . The pull-down circuit according to claim 11 , wherein the level shifter includes
a second PMOS transistor connected between a node through which the level shifter output voltage is output and an output terminal of the charge pump circuit, and configured to receive the one-shot signal through a gate thereof.

20 . The pull-down circuit according to claim 11 , wherein the sink circuit includes a sink transistor, and
the level shifter includes a voltage clamping circuit connected between a gate and a source of the sink transistor, and configured to limit a voltage level to be applied to the sink transistor.

Assignees

• Sk Hynix Inc

Inventors

• Lee Junghan
• Lee Jin Seok

Classifications

• H02M1/32

  Means for protecting converters other than automatic disconnection · CPC title

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H03K19/018521 Primary

  of complementary type, e.g. CMOS · CPC title

• H03K19/01721 Primary

  by means of a pull-up or down element · CPC title

• H02M3/073

  Charge pumps of the Schenkel-type · CPC title