Semiconductor memory device and method of operating the semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2025087271-A1
Application number	US-202418411348-A
Country	US
Kind code	A1
Filing date	Jan 12, 2024
Priority date	Sep 7, 2023
Publication date	Mar 13, 2025
Grant date	—

Abstract

Provided herein is a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a first string group including at least one first memory string and a second string group including at least one second memory string, each string connected in parallel between the bit line and the source line, wherein the at least one first memory string and the at least one second memory string each include at least one down source select transistor, at least one first up source select transistor, and at least one second up source select transistor, and the at least one first up source select transistor of the at least one first memory string is programmed to a first state, and the at least one first up source select transistor of the at least one second memory string is programmed to a second state different from the first state.

First claim

What is claimed is:

1 . A semiconductor memory device, comprising:
a first string group including a plurality of first memory strings connected in parallel between a bit line and a source line; and a second string group including a plurality of second memory strings connected in parallel between the bit line and the source line, wherein each of the plurality of first memory strings and the plurality of second memory strings includes at least one down source select transistor, at least one first up source select transistor, and at least one second up source select transistor, and wherein the at least one first up source select transistor of each of the plurality of first memory strings is programmed to a first state, and the at least one first up source select transistor of each of the plurality of second memory strings is programmed to a second state.

2 . The semiconductor memory device according to claim 1 , wherein the at least one second up source select transistor of each of the plurality of first memory strings is programmed to the second state, and the at least one second up source select transistor of each of the plurality of second memory strings is programmed to the first state.

3 . The semiconductor memory device according to claim 1 , wherein the first state is an erase state and the second state is a program state.

4 . The semiconductor memory device according to claim 1 , wherein a coding data value of the at least one first up source select transistor and the at least one second up source select transistor of the first string group is different from a coding data value of the at least one first up source select transistor and the at least one second up source select transistor of the second string group.

5 . The semiconductor memory device according to claim 1 , wherein:
each of the plurality of first memory strings and the plurality of second memory strings includes a drain select transistor coupled to the bit line, and the drain select transistors of the plurality of first memory strings and the plurality of second memory strings are electrically coupled to different drain select lines, respectively.

6 . The semiconductor memory device according to claim 1 , wherein:
at least one down source select transistor of the plurality of first memory strings and at least one down source select transistor of the plurality of second memory strings share one down source select line, at least one first up source select transistor of the plurality of first memory strings and at least one first up source select transistor of the plurality of second memory strings share one first up source select line, and at least one second up source select transistor of the plurality of first memory strings and at least one second up source select transistor of the plurality of second memory strings share one second up source select line.

7 . The semiconductor memory device according to claim 1 , wherein the plurality of first memory strings and the plurality of second memory strings are alternately arranged.

8 . A method of operating a semiconductor memory device including a plurality of first memory strings and a plurality of second memory strings, each of the first and second memory strings are connected in parallel between a bit line and a source line, each of the first and second memory strings including at least one first up source select transistor and at least one second up source select transistor which are connected in series, comprising:
programming the at least one second up source select transistor of the plurality of first memory strings to a first state; programming the at least one second up source select transistor of the plurality of second memory strings to a second state; programming the at least one first up source select transistor of the plurality of first memory strings to the second state; and programming the at least one first up source select transistor of the plurality of second memory strings to the first state, wherein the at least one first up source select transistor of the plurality of first memory strings and the at least one first up source select transistor of the plurality of second memory strings are programed based on a first up source select line, and wherein the at least one second up source select transistor of the plurality of first memory strings and the at least one second up source select transistor of the plurality of second memory strings are programed based on a second up source select line.

9 . The method according to claim 8 , wherein each of the first and second memory strings further comprises at least one drain select transistor connected to the bit line, and
wherein programming the second up source select transistors of the first and second memory strings, comprises: applying a program-enable voltage to the bit line; applying a turn-off voltage to first drain select lines coupled to the drain select transistors of the plurality of first memory strings, and applying a turn-on voltage to second drain select lines coupled to the drain select transistors of the plurality of second memory strings; and applying a program voltage to the second up source select line, and applying a pass voltage to the first up source select line.

10 . The method according to claim 8 , wherein each of the first and second memory strings further comprises at least one drain select transistor connected to the bit line, and a plurality memory cells connected between the at least one drain select transistor and the at least one first up source select transistor, and
wherein programming the first up source select transistors of the first and second memory strings comprises: applying a program-enable voltage to the bit line; applying a turn-on voltage to first drain select lines coupled to drain select transistors of the plurality of first memory strings, and applying a turn-off voltage to second drain select lines coupled to drain select transistors of the plurality of second memory strings; and applying a program voltage to the first up source select line and applying a pass voltage to the second up source select line.

11 . The method according to claim 8 , wherein the first state includes programing data “1” to the at least one first up source transistor or the at least one second up source transistor, and
the second state includes programing data “0” to the at least one first up source transistor or the at least one second up source transistor.

12 . The method according to claim 8 , wherein a coding value of the first up source select transistors and the second up source select transistors of the plurality of first memory strings is programmed to be different from a coding value of the first up source select transistors and the second up source select transistors of the plurality of second memory strings.

13 . The method according to claim 8 , wherein the plurality of first memory strings and the plurality of second memory strings are alternately arranged.

14 . A semiconductor memory device, comprising:
a plurality of first memory strings connected in parallel between a bit line and a source line; and a plurality of second memory strings connected in parallel between the bit line and the source line, wherein each of the plurality of first memory strings and the plurality of second memory strings includes at least one down source select transistor, at least one first up source select transistor, and at least one second up source select transistor which are connected in series, wherein at least one down source select transistor of the plurality of first memory strings a

Assignees

• Sk Hynix Inc

Inventors

• Lee Hee Youl

Classifications

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/34 Primary

  Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title