Display substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-2025087152-A1
Application number	US-202218558265-A
Country	US
Kind code	A1
Filing date	Dec 19, 2022
Priority date	Dec 19, 2022
Publication date	Mar 13, 2025
Grant date	—

Abstract

A display substrate includes an array substrate including pixels and pixel driving circuits. A pixel driving circuit includes a driving sub-circuit and a storage sub-circuit. The storage sub-circuit includes: a first capacitor coupled to a first node and a second node, and a second capacitor coupled to the second node and a first voltage signal terminal. The driving sub-circuit is configured to generate a driving current under control of the storage sub-circuit and transmit the driving current to a light-emitting device. In a direction perpendicular to the array layer, the first plate, the second plate, the third plate and the fourth plate have an overlapping region therebetween.

First claim

1 . A display substrate, comprising:
an array layer, the array layer including a plurality of pixels and a plurality of pixel driving circuits corresponding to the plurality of pixels; wherein a pixel driving circuit includes a driving sub-circuit and a storage sub-circuit; wherein
the storage sub-circuit includes a first capacitor and a second capacitor connected in series; a first plate of the first capacitor is coupled to a first node, and a second plate of the first capacitor is coupled to a second node; a third plate of the second capacitor is coupled to the second node, and a fourth plate of the second capacitor is coupled to a first voltage signal terminal; and
the driving sub-circuit is coupled to the first node, the second node and a third node, and the driving sub-circuit is configured to generate a driving current under control of the storage sub-circuit and transmit the driving current to a light-emitting device;
wherein in a direction perpendicular to the array layer, the first plate, the second plate, the third plate and the fourth plate have an overlapping region therebetween.

2 . The display substrate according to claim 1 , wherein the driving sub-circuit includes a driving transistor; a gate of the driving transistor is coupled to the first node, a first electrode of the driving transistor is coupled to the second node, and a second electrode of the driving transistor is coupled to the third node.

3 . The display substrate according to claim 1 , wherein the pixel driving circuit further includes a writing sub-circuit; the writing sub-circuit is coupled to a data signal terminal, a first scan signal terminal and the first node; the writing sub-circuit is configured to: transmit a first data signal received at the data signal terminal to the first node under control of a first scan signal received from the first scan signal terminal in an initialization period; and transmit a second data signal received at the data signal terminal under control of the first scan signal received from the first scan signal terminal in a data writing period.

4 . The display substrate according to claim 3 , wherein the writing sub-circuit includes a first transistor; a gate of the first transistor is coupled to the first scan signal terminal, a first electrode of the first transistor is coupled to the data signal terminal, and a second electrode of the first transistor is coupled to the first node.

5 . The display substrate according to claim 1 , wherein the pixel driving circuit further includes a light-emitting control sub-circuit;
the light-emitting control sub-circuit is coupled to the first voltage signal terminal, a second scan signal terminal and the second node; the light-emitting control sub-circuit is configured to transmit a first voltage signal at the first voltage signal terminal to the second node under control of a second scan signal from the second scan signal terminal in an initialization period and a light-emitting period.

6 . The display substrate according to claim 5 , wherein the light-emitting control sub-circuit includes a second transistor; a gate of the second transistor is coupled to the second scan signal terminal, a first electrode of the second transistor is coupled to the first voltage signal terminal, and a second electrode of the second transistor is coupled to the second node.

7 . The display substrate according to claim 1 , wherein the pixel driving circuit further includes a reset sub-circuit;
the reset sub-circuit is coupled to a third scan signal terminal, a second voltage signal terminal and the third node; the reset sub-circuit is configured to transmit a second voltage signal at the second voltage signal terminal to the third node under control of a third scan signal from the third scan signal terminal in a light-emitting period.

8 . The display substrate according to claim 7 , wherein the reset sub-circuit includes a third transistor; a gate of the third transistor is coupled to the third scan signal terminal, a first electrode of the third transistor is coupled to the second voltage signal terminal, and a second electrode of the third transistor is coupled to the third node.

9 . The display substrate according to claim 8 , wherein the driving sub-circuit includes a driving transistor, the pixel driving circuit further includes a first transistor, and a second transistor,
the array layer includes a silicon substrate, and a first source-drain metal layer and a first gate metal layer that are sequentially stacked on the silicon substrate; a first electrode and a second electrode of the first transistor, a first electrode and a second electrode of the second transistor, the first electrode and the second electrode of the third transistor, and a first electrode and a second electrode of the driving transistor are all located in the first source-drain metal layer; and a gate of the first transistor, a gate of the second transistor, the gate of the third transistor, and a gate of the driving transistor are all located in the first gate metal layer.

10 . The display substrate according to claim 8 , wherein the driving sub-circuit includes a driving transistor, the pixel driving circuit further includes, a first transistor and a second transistor,
the first transistor, the second transistor and the driving transistor are P-type transistors; the first transistor, the second transistor and the driving transistor are all located in an N-well region of the silicon substrate; and the third transistor is an N-type transistor; the third transistor is located in a deep N-well region of the silicon substrate.

11 . The display substrate according to claim 10 , wherein the deep N-well region includes a first doped region and a second doped region; doped ions in the first doped region are N ions, and doped ions in the second doped region are P ions; wherein
the first doped region includes a first sub-region and a second sub-region, the first electrode of the third transistor is electrically connected to the first sub-region, and the second electrode of the third transistor is electrically connected to the second sub-region; the second doped region is electrically connected to the second voltage signal terminal.

12 . The display substrate according to claim 8 , wherein the driving sub-circuit includes a driving transistor, in a case where the pixel driving circuit further includes a first transistor and, a second transistor,
in a pixel of the plurality of pixels, in a first direction, a third transistor is located on a side of a driving transistor, and both a first transistor and a second transistor are located on another side of the driving transistor; the plurality of pixels include first pixels and second pixels alternately arranged in a second direction; in an adjacent first pixel and second pixel, a third transistor in the first pixel is arranged adjacent to a third transistor in the second pixel; wherein the first direction and the second direction intersect.

13 . The display substrate according to claim 12 , wherein in the pixel, the first transistor and the second transistor are arranged in the second direction; and/or
in the adjacent first pixel and second pixel, a first electrode of the third transistor in the first pixel is coupled to a first electrode of the third transistor in the second pixel.

14 . (canceled)

15 . The display substrate according to claim 12 , wherein in a previous first pixel, a second pixel and a next first pixel arranged in the second direction,
a first transistor in the previous first pixel is arranged adjacent to a first transistor in the sec

Assignees

• Yunnan Invensight Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Fan Longfei
• Ma Yaoxi
• Li Dachao
• Jiang Shanghong
• Lu Pengcheng
• Yang Shengji
• Chen Xiaochuan

Classifications

• G09G2320/0209

  Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display · CPC title

• G09G2320/0219

  Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2310/0251

  Precharge or discharge of pixel before applying new pixel voltage · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title