Pixel circuit and driving method therefor, array substrate, and display apparatus

Patent metadata

Field	Value
Publication number	US-2025087151-A1
Application number	US-202218558257-A
Country	US
Kind code	A1
Filing date	Dec 9, 2022
Priority date	Dec 9, 2022
Publication date	Mar 13, 2025
Grant date	—

Abstract

A pixel circuit includes a driving transistor, a reset sub-circuit, a leakage prevention sub-circuit and a data writing sub-circuit. The reset sub-circuit is configured to, under control of a first scanning signal, transmit a reference voltage signal to a first electrode of the driving transistor. The leakage prevention sub-circuit is configured to, under control of a second scanning signal, connect the first electrode of the driving transistor to a control electrode of the driving transistor. The data writing sub-circuit is configured to, under control of a third scanning signal, transmit a data signal to a second electrode of the driving transistor. The reset sub-circuit and the data writing sub-circuit are turned on sequentially when the leakage prevention sub-circuit is turned on; and the reset sub-circuit is turned on at least once when the leakage prevention sub-circuit is turned off.

First claim

1 . A pixel circuit, comprising:
a driving transistor including a control electrode, a first electrode and a second electrode; a reset sub-circuit, electrically connected to a first scanning signal terminal, a reference voltage signal terminal and the first electrode of the driving transistor, and configured to, under control of a first scanning signal from the first scanning signal terminal, transmit a reference voltage signal from the reference voltage signal terminal to the first electrode of the driving transistor; a leakage prevention sub-circuit, electrically connected to a second scanning signal terminal, and the first electrode and the control electrode of the driving transistor, and configured to, under control of a second scanning signal from the second scanning signal terminal, connect the first electrode of the driving transistor to the control electrode of the driving transistor; and a data writing sub-circuit, electrically connected to a third scanning signal terminal, a data signal terminal and the second electrode of the driving transistor, and configured to, under control of a third scanning signal from the third scanning signal terminal, transmit a data signal from the data signal terminal to the second electrode of the driving transistor, wherein the reset sub-circuit and the data writing sub-circuit are configured to, under the control of respective scanning signals, be turned on sequentially in a case where the leakage prevention sub-circuit is turned on; and the reset sub-circuit is configured to, under the control of the first scanning signal, be turned on at least once in a case where the leakage prevention sub-circuit is turned off.

2 . The pixel circuit according to claim 1 , wherein
the reset sub-circuit includes a first transistor, wherein a control electrode of the first transistor is electrically connected to the first scanning signal terminal, a first electrode of the first transistor is electrically connected to the reference voltage signal terminal, and a second electrode of the first transistor is electrically connected to the first electrode of the driving transistor; the leakage prevention sub-circuit includes a second transistor, wherein a control electrode of the second transistor is electrically connected to the second scanning signal terminal, a first electrode of the second transistor is electrically connected to the first electrode of the driving transistor, and a second electrode of the second transistor is electrically connected to the control electrode of the driving transistor; and the data writing sub-circuit includes a third transistor, wherein a control electrode of the third transistor is electrically connected to the third scanning signal terminal, the first electrode of the third transistor is electrically connected to the data signal terminal, and the second electrode of the third transistor is electrically connected to the second electrode of the driving transistor.

3 . The pixel circuit according to claim 2 , wherein the second transistor is a metal oxide thin film transistor; and
the first transistor, the third transistor and the driving transistor are low temperature polysilicon thin film transistors.

4 . (canceled)

5 . The pixel circuit according to claim 1 , wherein in the case where the leakage prevention sub-circuit is turned off, the data writing sub-circuit is configured to, under the control of the third scanning signal, be turned on at least once, and the data signal terminal is configured to output a first reset voltage signal.

6 . The pixel circuit according to claim 1 , further comprising:
a first control sub-circuit, electrically connected to a light-emitting control signal terminal, a first voltage signal terminal and the first electrode of the driving transistor, and configured to, under control of a light-emitting control signal from the light-emitting control signal terminal, transmit a first voltage signal from the first voltage signal terminal to the first electrode of the driving transistor; a second control sub-circuit, electrically connected to the light-emitting control signal terminal and the second electrode of the driving transistor, wherein the second control sub-circuit is configured to be electrically connected to a light-emitting device, and under the control of the light-emitting control signal, transmit a driving current from the driving transistor to the light-emitting device; an unset sub-circuit, electrically connected to the first scanning signal terminal; and an initialization signal terminal, wherein the unset sub-circuit is configured to be electrically connected to the light-emitting device, and under the control of the first scanning signal, transmit an initialization signal from the initialization signal terminal to the light-emitting device; and an energy storage sub-circuit, electrically connected to the control electrode of the driving transistor and the first voltage signal terminal, and configured to maintain a voltage of the control electrode of the driving transistor.

7 . The pixel circuit according to claim 6 , wherein
the first control sub-circuit includes a fourth transistor, wherein a control electrode of the fourth transistor is electrically connected to the light-emitting control signal terminal, a first electrode of the fourth transistor is electrically connected to the first voltage signal terminal, and a second electrode of the fourth transistor is electrically connected to the first electrode of the driving transistor; the second control sub-circuit includes a fifth transistor, wherein a control electrode of the fifth transistor is electrically connected to the light-emitting control signal terminal, a first electrode of the fifth transistor is electrically connected to the second electrode of the driving transistor, and a second electrode of the fifth transistor is configured to be electrically connected to the light-emitting device; the reset sub-circuit includes a sixth transistor, wherein a control electrode of the sixth transistor is electrically connected to the first scanning signal terminal, a first electrode of the sixth transistor is electrically connected to the initialization signal terminal, and a second electrode of the sixth transistor is configured to be electrically connected to the light-emitting device; and the energy storage sub-circuit includes a storage capacitor, wherein a first electrode plate of the storage capacitor is electrically connected to the control electrode of the driving transistor, and a second electrode plate of the storage capacitor is electrically connected to the first voltage signal terminal.

8 . A driving method for the pixel circuit according to claim 1 , a display frame including an unset phase, a data writing phase and a first reset phase; the driving method comprising:
in the unset phase: outputting, by the first scanning signal terminal and the second scanning signal terminal, operating levels; outputting, by the third scanning signal terminal, a non-operating level; and transmitting the reference voltage signal from the reference voltage signal terminal to the control electrode of the driving transistor via the reset sub-circuit and the leakage prevention circuit; in the data writing phase: outputting, by the first scanning signal terminal, a non-operating level; outputting, by the second scanning signal terminal and the third scanning signal terminal, operating levels; outputting, by the data signal terminal, the data signal; transmitting the data signal to the second electrode of the driving transistor via the data writing sub-circuit; and writing the data signal and a threshold voltage to the control electrode of the driving transistor; and in the first reset phase: outputting, by t

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Wang Zhu
• Shang Yanyang
• Yan Zhenglong
• Shi Ling

Classifications

• H10K59/1216

  the pixel elements being capacitors · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title