Apparatuses and methods for configurable memory array bank architectures

Patent metadata

Field	Value
Publication number	US-2025085847-A1
Application number	US-202418956551-A
Country	US
Kind code	A1
Filing date	Nov 22, 2024
Priority date	Jun 28, 2018
Publication date	Mar 13, 2025
Grant date	—

Abstract

Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.

First claim

What is claimed is:

1 . A method comprising:
providing a clock signal to a memory; providing a mode register write command and a value to be written to a mode register of the memory to set a frequency set point of a plurality of frequency set points of the memory; provide a first read command and a first address; and provide a second read command and a second address at least a number of clock cycles after the first read command, the number of clock cycles based, at least in part, on a bank architecture set in the memory wherein the bank architecture is based, at least in part, on the frequency set point.

2 . The method of claim 1 , further comprising:
receiving first data associated with the first read command; and providing second data associated with the second read command.

3 . The method of claim 1 , wherein the number of clock cycles is further based on a burst length of the bank architecture.

4 . The method of claim 3 , wherein the bank architecture is a bank group mode, and the number of clock cycles is at least two clock cycles when the burst length is sixteen.

5 . The method of claim 3 , wherein the number of clock cycles is at least four clock cycles when the burst length is thirty-two.

6 . The method of claim 1 , wherein the number of clock cycles is further based on whether the first address and the second address are in a same bank group.

7 . The method of claim 6 , wherein the number of clock cycles is at least four clock cycles when the first address and the second address are for the same bank group.

8 . The method of claim 7 , wherein the number of clock cycles is at least two clock cycles when the first address and the second address are for different bank groups.

9 . The method of claim 1 , wherein the number of clock cycles is at least two clock cycles.

10 . The method of claim 1 , wherein the number of clock cycles is at least four clock cycles.

11 . The method of claim 1 , further comprising:
providing a third read command; receiving first data responsive to the first read command; receiving second data responsive to the second read command; and receiving third data responsive to the third read command.

12 . The method of claim 11 , further comprising receiving fourth data responsive to the third read command at least two clock cycles of the clock signal after providing the third data.

13 . An apparatus comprising:
a controller configured to: provide a system clock signal to a memory; provide a first read command; provide a second read command, wherein the second read command is provided at least a number of clock cycles after the first read command; provide a first address and a second address associated with the first and second read commands;
provide a mode register write command and a first value to set a bank architecture from a plurality of bank architectures and a second value to set a frequency set point from a plurality of frequency set points, wherein the first value is configured to be changed by changing the second value, wherein the number of clock cycles is based at least in part, on the bank architecture;
receive first data responsive to the first read command; and receive second data responsive to the second read command.

14 . The apparatus of claim 13 , wherein the plurality of bank architectures comprises a bank mode and a bank group mode.

15 . The apparatus of claim 13 , wherein the number of clock cycles is at least two clock cycles when a burst length is sixteen and the number of clock cycles is at least four clock cycles when the burst length is thirty-two.

16 . The apparatus of claim 13 , wherein when the bank architecture comprises the bank group mode, and wherein the number of clock cycles is at least four clock cycles when the first address and the second address are for the same bank group and the number of clock cycles is at least two clock cycles when the first address and the second address are for different bank groups.

17 . The apparatus of claim 16 , wherein the number of clock cycles is at least two clock cycles when the first address and the second address are for different bank groups.

18 . The apparatus of claim 13 , wherein the number of clock cycles is at least two clock cycles or at least four clock cycles.

19 . The apparatus of claim 13 , wherein when the bank architecture comprises the bank group mode and the first and second read commands are for different bank groups, the controller is configured to receive sixteen bits of data from a first bank group followed by sixteen bits of data from a second bank group.

20 . The apparatus of claim 19 , wherein when a burst length is thirty-two bits, the controller is further configured to receive a second sixteen bits of data from the first bank group followed by another sixteen bits of data from the second bank group.

Assignees

• Lodestar Licensing Group Llc

Inventors

• Gans Dean D
• Saito Shunichi

Classifications

• G06F3/0629

  Configuration or reconfiguration of storage systems · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F2212/1012

  Design facilitation · CPC title

• G06F12/10

  Address translation · CPC title

• G06F2212/7202

  Allocation control and policies · CPC title