Predicting local layout effects using a variational autoencoder with integrated regression and classification network

Patent metadata

Field	Value
Publication number	US-2025077888-A1
Application number	US-202318459803-A
Country	US
Kind code	A1
Filing date	Sep 1, 2023
Priority date	Sep 1, 2023
Publication date	Mar 6, 2025
Grant date	—

Abstract

Predicting local layout effects using a variational autoencoder with integrated regression and classification network including identifying a vector of features and a vector of output metrics from a dataset; performing basic training of a neural network machine learning variational autoencoder (VAE) combined with a regression network using the vector of features and the vector of output targets constrained to a latent space of the VAE; performing interpolation training of the VAE and combined regression network; determining a set of influential features of an integrated circuit layout based on an input gradient using an output of the VAE and combined regression network with interpolation training; using the set of influential features as input into a parallel neural network to generate a function for each influential feature; and creating a compact model to calculate local layout effects based on the functions for each influential feature.

First claim

What is claimed is:

1 . A method for predicting local layout effects using a variational autoencoder with integrated regression and classification network, the method comprising:
identifying a dataset from a database of integrated circuit layouts of integrated circuits and electrical measurements of the integrated circuits; identifying a vector of features and a vector of output metrics from the dataset; performing basic training of a neural network machine learning variational autoencoder (VAE) combined with a regression network using the vector of features and the vector of output targets constrained to a latent space of the VAE; performing interpolation training of the VAE and combined regression network using the vector of features and the vector of output metrics to generate interpolated vectors for interpolation training; determining a set of influential features of an integrated circuit layout based on an input gradient using an output of the VAE and combined regression network with interpolation training; using the set of influential features as input into a parallel neural network to generate a function for each influential feature; and creating a compact model to calculate local layout effects based on the functions for each influential feature.

2 . The method of claim 1 , further comprising:
determining that the influential features of the integrated circuit layout are within a domain of training data points in latent space by examining a location of a test data point relative to training data points in the latent space.

3 . The method of claim 1 , wherein the integrated circuit layout is a layer of an integrated circuit design.

4 . The method of claim 1 , wherein the compact model is based on a sum of the functions for each influential feature.

5 . The method of claim 1 , wherein the functions for each influential feature are magnitudes of effects on an electrical parameter.

6 . The method of claim 1 , wherein the local layout effects comprise one from a group consisting of threshold voltage, drive current, circuit power, and circuit delay.

7 . The method of claim 1 , wherein the local layout effects comprise one from a group consisting of yield, defectively, measured line width, and measured space.

8 . An apparatus for predicting local layout effects using a variational autoencoder with integrated regression and classification network, the apparatus comprising:
a computer processor; and a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to:
identifying a dataset from a database of integrated circuit layouts of integrated circuits and electrical measurements of the integrated circuits;
identifying a vector of features and a vector of output metrics from the dataset;
performing basic training of a neural network machine learning variational autoencoder (VAE) combined with a regression network using the vector of features and the vector of output targets constrained to a latent space of the VAE;
performing interpolation training of the VAE and combined regression network using the vector of features and the vector of output metrics to generate interpolated vectors for interpolation training;
determining a set of influential features of an integrated circuit layout based on an input gradient using an output of the VAE and combined regression network with interpolation training;
using the set of influential features as input into a parallel neural network to generate a function for each influential feature; and
creating a compact model to calculate local layout effects based on the functions for each influential feature.

9 . The apparatus of claim 8 , wherein the computer program instructions further cause the apparatus to carry out the step of:
determining that the influential features of the integrated circuit layout are within a domain of training data points in latent space by examining a location of a test data point relative to training data points in the latent space.

10 . The apparatus of claim 8 , wherein the integrated circuit layout is a layer of an integrated circuit design.

11 . The apparatus of claim 8 , wherein the compact model is based on a sum of the functions for each influential feature.

12 . The apparatus of claim 8 , wherein the functions for each influential feature are magnitudes of effects on an electrical parameter.

13 . The apparatus of claim 8 , wherein the local layout effects comprise one from a group consisting of threshold voltage, drive current, circuit power, and circuit delay.

14 . The apparatus of claim 8 , wherein the local layout effects comprise one from a group consisting of yield, defectively, measured line width, and measured space.

15 . A computer program product for predicting local layout effects using a variational autoencoder with integrated regression and classification network, the computer program product disposed upon a computer readable medium, the computer program product comprising computer program instructions that, when executed, cause a computer to:
identify a dataset from a database of integrated circuit layouts of integrated circuits and electrical measurements of the integrated circuits; identify a vector of features and a vector of output metrics from the dataset; perform basic training of a neural network machine learning variational autoencoder (VAE) combined with a regression network using the vector of features and the vector of output targets constrained to a latent space of the VAE; perform interpolation training of the VAE and combined regression network using the vector of features and the vector of output metrics to generate interpolated vectors for interpolation training; determine a set of influential features of an integrated circuit layout based on an input gradient using an output of the VAE and combined regression network with interpolation training; use the set of influential features as input into a parallel neural network to generate a function for each influential feature; and create a compact model to calculate local layout effects based on the functions for each influential feature.

16 . The computer program product of claim 15 , wherein the computer program instructions further cause the apparatus to carry out the step of:
determining that the influential features of the integrated circuit layout are within a domain of training data points in latent space by examining a location of a test data point relative to training data points in the latent space.

17 . The computer program product of claim 15 , wherein the integrated circuit layout is a layer of an integrated circuit design.

18 . The computer program product of claim 15 , wherein the compact model is based on a sum of the functions for each influential feature.

19 . The computer program product of claim 15 , wherein the functions for each influential feature are magnitudes of effects on an electrical parameter.

20 . The computer program product of claim 15 , wherein the local layout effects comprise one from a group consisting of threshold voltage. drive current, circuit power, and circuit delay.

Assignees

• IBM

Inventors

• Monkowski Michael Daniel
• Kazda Michael
• Wegman Mark
• Wachnik Richard Andre

Classifications

• G06N3/088

  Non-supervised learning, e.g. competitive learning · CPC title

• G06N3/047

  Probabilistic or stochastic networks · CPC title

• G06N3/045

  Combinations of networks · CPC title

• G06N3/098 Primary

  Distributed learning, e.g. federated learning · CPC title

• G06N3/0455 Primary

  Auto-encoder networks; Encoder-decoder networks · CPC title