Display panel and method for manufacturing the same

US2025072226A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2025072226-A1
Application numberUS-202418749749-A
CountryUS
Kind codeA1
Filing dateJun 21, 2024
Priority dateAug 25, 2023
Publication dateFeb 27, 2025
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A display panel includes: a base layer; a first electrode disposed on the base layer; a pixel-defining film in which a light-emitting opening partially exposing the first electrode is defined, and which is disposed on the base layer; a first conductive partition wall in which a first partition wall opening overlapping the light-emitting opening in a plan view is defined, and which is disposed on the pixel-defining film; a second conductive partition wall in which a second partition wall opening overlapping the first partition wall opening, and a dummy opening overlapping the first conductive partition wall in the plan view are defined, and which is disposed on the first conductive partition wall; a second electrode disposed on the first electrode, and a light-emitting pattern disposed between the first electrode and the second electrode.

First claim

Opening claim text (preview).

What is claimed is: 1 . A display panel comprising: a base layer; a first electrode disposed on the base layer; a pixel-defining film in which a light-emitting opening partially exposing the first electrode is defined, and which is disposed on the base layer; a first conductive partition wall in which a first partition wall opening overlapping the light-emitting opening in a plan view is defined, and which is disposed on the pixel-defining film; a second conductive partition wall in which a second partition wall opening overlapping the first partition wall opening, and a dummy opening overlapping the first conductive partition wall in the plan view are defined, and which is disposed on the first conductive partition wall; a second electrode disposed on the first electrode; and a light-emitting pattern disposed between the first electrode and the second electrode. 2 . The display panel of claim 1 , further comprising an inorganic lower encapsulation pattern disposed on the second electrode, and configured to cover the light-emitting opening, the first partition wall opening, and the second partition wall opening. 3 . The display panel of claim 2 , further comprising an inorganic intermediate encapsulation film configured to cover the dummy opening and an upper surface of the second conductive partition wall. 4 . The display panel of claim 3 , wherein an upper surface of the first conductive partition wall exposed by the dummy opening is in contact with the inorganic intermediate encapsulation film. 5 . The display panel of claim 3 , wherein a side surface defining the second partition wall opening of the second conductive partition wall is in contact with the inorganic lower encapsulation pattern, and a side surface defining the dummy opening of the second conductive partition wall is in contact with the inorganic intermediate encapsulation film. 6 . The display panel of claim 1 , wherein the dummy opening is provided in plurality. 7 . The display panel of claim 1 , wherein the first conductive partition wall comprises a first lower layer disposed on the pixel-defining film and a second lower layer disposed on the first lower layer, and a side surface of the second lower layer protrudes further than a side surface of the first lower layer in the plan view. 8 . The display panel of claim 1 , wherein the second conductive partition wall comprises a first upper layer disposed on the first conductive partition wall and a second upper layer disposed on the first upper layer, and a side surface of the second upper layer protrudes further than a side surface of the first upper layer in the plan view. 9 . The display panel of claim 1 , wherein the second electrode is in contact with a side surface of the first conductive partition wall to be electrically connected to each other. 10 . The display panel of claim 1 , wherein a bias voltage is applied to the first conductive partition wall. 11 . The display panel of claim 2 , further comprising an inorganic dummy encapsulation film configured to cover the dummy opening. 12 . The display panel of claim 11 , further comprising a dummy pattern disposed on the first conductive partition wall in the dummy opening. 13 . The display panel of claim 12 , wherein the dummy pattern is not in contact with the second conductive partition wall. 14 . The display panel of claim 11 , wherein a side surface defining the second partition wall opening of the second conductive partition wall is in contact with the inorganic lower encapsulation pattern, and a side surface defining the dummy opening of the second conductive partition wall is in contact with the inorganic dummy encapsulation film. 15 . A method for manufacturing a display panel, the method comprising: preparing a preliminary display panel including a base layer, a first conductive electrode disposed on the base layer, a preliminary pixel-defining film configured to cover the first electrode and disposed on the base layer, a first conductive layer disposed on the preliminary pixel-defining film, and a second conductive layer disposed on the first conductive layer; patterning photoresist on the preliminary display panel; forming a second preliminary partition wall opening in the second conductive layer; forming a first preliminary conductive partition wall by forming, in the first conductive layer, a first preliminary partition wall opening overlapping the second preliminary partition wall opening in a plan view; forming a second preliminary conductive partition wall by forming, in the second conductive layer, a preliminary dummy opening spaced apart from the second partition wall opening; forming a light-emitting pattern on the first electrode; and forming a second electrode on the light-emitting pattern, wherein in the patterning of the photoresist, the photoresist is patterned to have a first thickness in a first region overlapping neither the second preliminary partition wall opening nor the preliminary dummy opening in the plan view, the photoresist is patterned to have a second thickness smaller than the first thickness in a second region overlapping the preliminary dummy opening in the plan view, and the photoresist is patterned not to be disposed in a third region overlapping the second preliminary partition wall opening in the plan view. 16 . The method of claim 15 , wherein the forming of the second preliminary partition wall opening comprises forming the second conductive layer corresponding to the third region by dry-etching, the forming of the second preliminary conductive partition wall comprises removing the photoresist corresponding to the second region by ashing the photoresist, and dry-etching the second conductive layer corresponding to the second region, and the forming of the first preliminary conductive partition wall comprises dry-etching the first conductive layer corresponding to the third region. 17 . The method of claim 15 , further comprising forming a first conductive partition wall defining a first partition wall opening and a second conductive partition wall defining a second partition wall opening by wet-etching side surfaces of the first preliminary conductive partition wall and the second preliminary conductive partition wall, wherein the first preliminary conductive partition wall includes a first preliminary lower layer disposed on the preliminary pixel-defining film and a second preliminary lower layer disposed on the first preliminary lower layer, the second preliminary conductive partition wall includes a first preliminary upper layer and a second preliminary upper layer disposed on the first preliminary upper layer, an etch rate of the first preliminary lower layer is greater than an etch rate of the second preliminary lower layer, and an etch rate of the first preliminary upper layer is greater than an etch rate of the second preliminary upper layer. 18 . The method of claim 17 , further comprising forming a pixel-defining film in which a light-emitting opening is defined by dry-etching the preliminary pixel-defining film corresponding to the first partition wall opening. 19 . The method of claim 18 , further comprising forming, on the second electrode, an inorganic lower encapsulation pattern configured to cover the light-emitting opening, the first partition wall opening, and the second partition wall opening. 20 . The method of claim 17 , further comprising forming an inorganic intermediate encapsulation film configured

Assignees

Inventors

Classifications

  • Providing a shape to conductive layers, e.g. patterning or selective deposition · CPC title

  • Manufacture or treatment · CPC title

  • Interconnections, e.g. wiring lines or terminals · CPC title

  • Encapsulations · CPC title

  • Dummy elements, i.e. elements having non-functional features · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2025072226A1 cover?
A display panel includes: a base layer; a first electrode disposed on the base layer; a pixel-defining film in which a light-emitting opening partially exposing the first electrode is defined, and which is disposed on the base layer; a first conductive partition wall in which a first partition wall opening overlapping the light-emitting opening in a plan view is defined, and which is disposed o…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10K59/122. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Feb 27 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).