Gaming Machines Having Retrofittable Insertable Memory Expansion Board with Onboard Random Number Generator

Patent metadata

Field	Value
Publication number	US-2025069469-A1
Application number	US-202418937217-A
Country	US
Kind code	A1
Filing date	Nov 5, 2024
Priority date	Jun 26, 2019
Publication date	Feb 27, 2025
Grant date	—

Abstract

A gaming device comprises a main board comprising a processor, a memory storing system program code and an expansion port in data communication with a memory interface of the processor, and a memory expansion board connected to the main board via the expansion port. The memory expansion board comprises a device configured to execute a random number generator and write random numbers into one or more registers of the memory expansion board accessible by the main board, and at least one connector for connecting a memory module comprising game program code. When the processor requires random numbers, the system program code causes the processor to read random numbers from the one or more registers of the memory expansion board.

First claim

What is claimed is:

1 . A gaming device comprising:
an expansion board having a hardware random number generator operable to generate a first random number, and a plurality of registers operable to store the first random number; and a main board comprising an expansion port operable to removably receive the expansion board, a processor, and a memory storing a plurality of system codes including a second random number generator, the system codes, which, when executed, causes the processor to at least:
when connected, access one or more of the plurality of registers on the expansion board for the first random number generated by the hardware random number generator,
generate via the second random number generator a second random number with the first random number read as a source of entropy for the second random number generator, and
determine a game outcome based on the second random number.

2 . The gaming device of claim 1 , wherein the hardware random number generator comprises a programmable logic device.

3 . The gaming device of claim 1 , wherein the memory further comprises a plurality of game codes, and the game codes, when executed, cause the processor to request a plurality of random numbers provided by the system codes when generating the game outcome.

4 . The gaming device of claim 1 , wherein the first random number comprises a first part written into a first register, and a second part written into a second register, and the system codes, when executed, further cause the processor to access the first register and the second register for the first random number.

5 . The gaming device of claim 1 , wherein the expansion board further comprises a second processor operable to seed the hardware random number generator to produce the first random number.

6 . The gaming device of claim 1 , wherein the processor accesses one or more of the plurality of registers at a request rate, and wherein the hardware random number generator is operable to produce a plurality of random numbers at a rate in excess of the request rate required by the main board.

7 . The gaming device of claim 1 , wherein the system codes further comprise an updating system software, which, when executed, further causes the processor to access the plurality of registers for the first random number from the expansion board instead of the second random number.

8 . A method for generating a game outcome in a gaming device having an expansion board that has a hardware random number generator and a plurality of registers, and a main board comprising an expansion port operable to removably receive the expansion board, a processor, and a memory storing a plurality of system codes including a second random number generator, the method comprising:
in response to the expansion board having been received at the expansion port, generating a first random number at the hardware random number generator, storing the first random number at the plurality of registers, and accessing one or more of the plurality of registers on the expansion board for the first random number generated by the hardware random number generator; generating via the second random number generator a second random number with the first random number read as a source of entropy for the second random number generator; and determining the game outcome based on the second random number.

9 . The method of claim 8 , wherein the hardware random number generator comprises a programmable logic device.

10 . The method of claim 8 , wherein the expansion board further comprises a second processor, further comprising the second processor seeding the hardware random number generator to produce the first random number.

11 . The method of claim 8 , further comprising:
writing a first part of the first random number into a first register, and a second part into a second register; and accessing the first register and the second register for the source of entropy.

12 . The method of claim 8 , wherein the processor accesses one or more of the plurality of registers at a request rate, and wherein the hardware random number generator is operable to produce a plurality of random numbers at a rate in excess of the request rate required by the main board.

13 . The method of claim 8 , wherein the processor accesses one or more of the plurality of registers at a request rate, further comprising accessing the plurality of registers for the first random number from the expansion board instead of the second random number.

14 . The method of claim 8 , wherein the system codes further comprise an updating system software, further comprising accessing the plurality of registers for the first random number from the expansion board instead of the second random number.

15 . A non-transitory computer-readable medium comprising system codes for generating a game outcome in a gaming device having an expansion board that has a hardware random number generator and a plurality of registers, and a main board comprising an expansion port operable to removably receive the expansion board, a processor, and a memory storing a plurality of system codes including a second random number generator, the system codes, which, when executed, cause the processor to perform the steps of:
initializing the expansion board when the expansion board is received at the expansion port, resulting in an initialized expansion board; generating a first random number at the hardware random number generator to be stored in the plurality of registers on the initialized expansion board; accessing one or more of the plurality of registers on the initialized expansion board for the first random number; generating via the second random number generator a second random number with the first random number read as a source of entropy for the second random number generator; and determining the game outcome based on the second random number.

16 . The non-transitory computer-readable medium of claim 15 , wherein the hardware random number generator comprises a programmable logic device.

17 . The non-transitory computer-readable medium of claim 15 , further comprising a plurality of game codes, and the game codes, when executed, further cause the processor to perform the step of requesting a plurality of random numbers provided by the system codes when generating the game outcome.

18 . The non-transitory computer-readable medium of claim 15 , wherein the system codes, when executed, further cause the processor to perform the steps of:
writing a first part of the first random number written into a first register, and a second part into a second register; and accessing the first register followed by the second register for the source of entropy.

19 . The non-transitory computer-readable medium of claim 15 , wherein the system codes, when executed, further cause the processor to perform the step of producing a plurality of random numbers at a rate in excess of a request rate required by the main board.

20 . The non-transitory computer-readable medium of claim 15 , wherein the system codes, when executed, further cause the processor to perform the steps of:
accessing one or more of the plurality of registers at a request rate; and the hardware random number generator producing a plurality of random numbers at a rate in excess of the request rate required by the main board.

Assignees

• Aristocrat Technologies Au

Inventors

• Daranyi Sandor
• Perrow Shane
• Adams Tyson
• Slade Rodney

Classifications

• G07F17/3241

  Security aspects of a gaming system, e.g. detecting cheating, device integrity, surveillance (computer security G06F21/00) · CPC title

• G07F17/3223

  Architectural aspects of a gaming system, e.g. internal configuration, leader-follower, wireless communication · CPC title

• G07F17/3218

  wherein at least part of the system is portable · CPC title

• G07F17/3227 Primary

  Configuring a gaming machine, e.g. downloading personal settings, selecting working parameters · CPC title