Frequency control and tuning of modular devices

Patent metadata

Field	Value
Publication number	US-2025068950-A1
Application number	US-202318236047-A
Country	US
Kind code	A1
Filing date	Aug 21, 2023
Priority date	Aug 21, 2023
Publication date	Feb 27, 2025
Grant date	—

Abstract

Identify a plurality of candidate quantum computing chips to be arranged in a multi-chip quantum processor. Generate a current optimized tuning plan for the arrangement of the plurality of candidate quantum computing chips in the multi-chip quantum processor. Obtain results of tuning in accordance with the optimized tuning plan from at least one tuning system. Carry out tuning yield assessment based on results of the obtained tuning results. Repeat the steps of obtaining results and carrying out tuning yield assessment, based on tuning being incomplete and the current optimized tuning plan remaining viable.

First claim

What is claimed is:

1 . A method comprising:
identifying a plurality of candidate quantum computing chips to be arranged in a multi-chip quantum processor; generating a current optimized tuning plan for the arrangement of the plurality of candidate quantum computing chips in the multi-chip quantum processor; obtaining results of tuning in accordance with the optimized tuning plan from at least one tuning system; carrying out tuning yield assessment based on results of the obtained tuning results; and repeating the steps of obtaining results and carrying out tuning yield assessment, based on tuning being incomplete and the current optimized tuning plan remaining viable.

2 . The method of claim 1 , further comprising, responsive to a subsequent determination that the current optimized tuning plan no longer remains viable, generating a new optimized tuning plan and repeating, for the new optimized tuning plan, the steps of obtaining results and carrying out tuning yield assessment based on tuning being incomplete and the new optimized tuning plan remaining viable.

3 . The method of claim 1 , further comprising, responsive to a subsequent determination that tuning is complete, carrying out post-tuning analytics.

4 . The method of claim 1 , wherein, in the obtaining step, the results of the tuning comprise LASIQ (Laser Annealing of Stochastically Impaired Qubits) results.

5 . The method of claim 4 , wherein the results of the tuning are obtained at a central server computer from multiple LASIQ (Laser Annealing of Stochastically Impaired Qubits) machines.

6 . The method of claim 1 , wherein identifying the plurality of candidate quantum computing chips to be arranged in the multi-chip quantum processor comprises:
accessing a stock of available quantum computing chips; testing functional and coupling structures of each of said available quantum computing chips; carrying out laser annealing calibration based on results of said testing; determining a tuning range of each of the functional and coupling structures; based on results of said determining of the tuning range and parameters of the stock of available quantum computing chips, determining an acceptable initial resistance range for each of the functional and coupling structures; based on results of determining an acceptable initial resistance range and junction resistances of the stock of available quantum computing chips, accepting a first fraction of the available quantum computing chips as the plurality of candidate quantum computing chips to be arranged in the multi-chip quantum processor and rejecting a second fraction of the available quantum computing chips.

7 . The method of claim 1 , wherein generating the current optimized tuning plan for the arrangement of the plurality of candidate quantum computing chips in the multi-chip quantum processor comprises applying a linear chip build approach.

8 . The method of claim 7 , wherein applying the linear chip build approach comprises:
accessing a stock of available quantum computing chips; selecting, from the stock, a top ranked chip by estimated functional yield; finding, from the stock, a best neighbor candidate for the top ranked chip by yield, based on frequency perturbation of the coupling structures; and repeating the steps of selecting and finding until a full solution is achieved.

9 . The method of claim 1 , wherein generating the current optimized tuning plan for the arrangement of the plurality of candidate quantum computing chips in the multi-chip quantum processor comprises applying deterministic tuning.

10 . The method of claim 9 , wherein applying the deterministic tuning comprises:
accessing a specification of potential locations for the plurality of candidate quantum computing chips to be arranged in the multi-chip quantum processor; defining, based on the specification, frequencies of coupling structures and boundary functional structures for each potential location; populating, from a stock of acceptable quantum computing chips, the potential locations with ones of the acceptable quantum computing chips capable of tuning to the defined frequencies of coupling structures and boundary functional structures; and repeating the populating step until a full solution is achieved.

11 . The method of claim 1 , wherein generating the current optimized tuning plan for the arrangement of the plurality of candidate quantum computing chips in the multi-chip quantum processor comprises applying an ad hoc, subsection-based approach.

12 . The method of claim 11 , wherein applying the ad hoc, subsection-based approach comprises:
accessing a specification of potential locations for the plurality of candidate quantum computing chips to be arranged in the multi-chip quantum processor, wherein the specification includes fixed resonant links and is partially pre-populated; defining subsections within the specification, beginning on ones of the subsection corresponding to the partial pre-population; selecting, from a stock of acceptable quantum computing chips, one or more of the acceptable chips and matching coupling structures in a given one of the subsections until a solution is obtained; and repeating the selecting step for additional ones of the subsections until a full solution is achieved.

13 . A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising:
identifying a plurality of candidate quantum computing chips to be arranged in a multi-chip quantum processor; generating a current optimized tuning plan for the arrangement of the plurality of candidate quantum computing chips in the multi-chip quantum processor; obtaining results of tuning in accordance with the optimized tuning plan from at least one tuning system; carrying out tuning yield assessment based on results of the obtained tuning results; and repeating the steps of obtaining results and carrying out tuning yield assessment, based on tuning being incomplete and the current optimized tuning plan remaining viable.

14 . The computer program product of claim 13 , wherein the method performed by the processor further comprises responsive to a subsequent determination that the current optimized tuning plan no longer remains viable, generating a new optimized tuning plan and repeating, for the new optimized tuning plan, the steps of obtaining results and carrying out tuning yield assessment based on tuning being incomplete and the new optimized tuning plan remaining viable.

15 . A system comprising:
a memory; and at least one processor, coupled to said memory, and operative to:
identify a plurality of candidate quantum computing chips to be arranged in a multi-chip quantum processor;
generate a current optimized tuning plan for the arrangement of the plurality of candidate quantum computing chips in the multi-chip quantum processor;
obtain results of tuning in accordance with the optimized tuning plan from at least one tuning system;
carry out tuning yield assessment based on results of the obtained tuning results; and
repeat the obtaining of the results and the carrying out of the tuning yield assessment, based on tuning being incomplete and the current optimized tuning plan remaining viable.

16 . The system of claim 15 , wherein the at least one processor is further operative to, responsive to a subsequent determination that the current optimized tuning plan no longer remains viable, generate a new o

Assignees

• IBM

Inventors

• Zhang Eric
• Hertzberg Jared Barney

Classifications

• G06N10/80

  Quantum programming, e.g. interfaces, languages or software-development kits for creating or handling programs capable of running on quantum computers; Platforms for simulating or accessing quantum computers, e.g. cloud-based quantum computing · CPC title

• G06N10/40 Primary

  Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control · CPC title