Electronic device

Patent metadata

Field	Value
Publication number	US-2025063801-A1
Application number	US-202418934223-A
Country	US
Kind code	A1
Filing date	Oct 31, 2024
Priority date	Nov 26, 2020
Publication date	Feb 20, 2025
Grant date	—

Abstract

The disclosure provides an electronic device. The electronic device includes a substrate, a transistor, and a variable capacitor. The transistor is disposed on the substrate. The variable capacitor is disposed on the substrate and adjacent to the transistor. A material of the transistor and a material of the variable capacitor both a include a III-V semiconductor material. The electronic device of an embodiment of the disclosure may simplify manufacturing process, reduce costs, or reduce dimensions.

First claim

What is claimed is:

1 . An electronic device, comprising:
a substrate; a transistor disposed on the substrate; and a variable capacitor disposed on the substrate and adjacent to the transistor, wherein a material of the transistor and a material of the variable capacitor both comprise a III-V semiconductor material.

2 . The electronic device of claim 1 , wherein the transistor is a high electron mobility transistor and the variable capacitor is a variable capacitance diode.

3 . The electronic device of claim 2 , wherein the variable capacitor is a Schottky diode.

4 . The electronic device of claim 3 , wherein the variable capacitor comprises:
a first region of a heavily-doped semiconductor layer disposed on the substrate; a lightly-doped semiconductor layer disposed on the first region of the heavily-doped semiconductor layer; a first electrode disposed on the first region of the heavily-doped semiconductor layer and electrically connected to the first region of the heavily-doped semiconductor layer; and a second electrode disposed on the lightly-doped semiconductor layer.

5 . The electronic device of claim 4 , wherein a Schottky contact is formed between the second electrode and the lightly-doped semiconductor layer.

6 . The electronic device of claim 4 , wherein the transistor comprises:
a buffer layer disposed on the substrate, a first semiconductor material layer disposed on the buffer layer; a second semiconductor material layer disposed on the first semiconductor material layer; the first region and a second region of the heavily-doped semiconductor layer respectively disposed on the second semiconductor material layer; a gate disposed on the second semiconductor material layer; and a source and a drain respectively disposed on the first region and the second region of the heavily-doped semiconductor layer.

7 . The electronic device of claim 6 , wherein the gate is disposed between the first region and the second region of the heavily-doped semiconductor layer.

8 . The electronic device of claim 6 , wherein the gate is in contact with the second semiconductor material layer.

9 . The electronic device of claim 6 , wherein the source is regarded as the first electrode.

10 . The electronic device of claim 6 , wherein the first region and the second region of the heavily-doped semiconductor layer are physically separated from each other.

Assignees

• Innolux Corp

Inventors

• Ting Chin-Lung
• Chi Jen-Hai
• Tseng Chia-Ping
• Yeh Chen-Lin
• Wei Chung-Kuang
• Chou Cheng-Hsu

Classifications

• H10D84/0123

  Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs · CPC title

• H10D84/813

  Combinations of field-effect devices and capacitor only · CPC title

• H10D84/05 Primary

  using Group III-V technology · CPC title

• H10D30/475

  having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs · CPC title

• H10D1/64

  Variable-capacitance diodes, e.g. varactors · CPC title