Nitride semiconductor device comprising layered structure of active region and method for manufacturing the same

US2025063787A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2025063787-A1
Application numberUS-202418934303-A
CountryUS
Kind codeA1
Filing dateNov 1, 2024
Priority dateOct 5, 2018
Publication dateFeb 20, 2025
Grant date

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A nitride semiconductor device includes a channel layer, a barrier layer made of Al x In y Ga 1-x-y N (x>0, x+y≤1), an active region that has a layered structure including the channel layer and the barrier layer, an inactive region that is formed at the layered structure around the active region and that is a concave portion having a bottom portion that reaches the channel layer, a gate layer made of a nitride semiconductor selectively formed on the barrier layer in the active region, a gate electrode formed on the gate layer, a first insulating film that covers the gate electrode and that is in contact with the barrier layer in the active region, and a second insulating film that covers the first insulating film and that is in contact with the inactive region.

First claim

Opening claim text (preview).

What is claimed is: 1 . A nitride semiconductor device comprising: a GaN layer; an AlGaN layer formed on the GaN layer; a plurality of drain contacts and a plurality of source contacts formed over the AlGaN layer, the plurality of drain contacts and the plurality of source contacts arranged alternately in a first direction; a concave portion formed at an edge portion of the nitride semiconductor device in a cross-section viewed from a second direction orthogonal to the first direction in plan view, a bottom portion of the concave portion formed by the GaN layer; an active region that has a layered structure including the GaN layer and the AlGaN layer; an inactive region that is formed at the layered structure around the active region and that is the concave portion having the bottom portion that reaches the GaN layer; a gate layer that is formed on the AlGaN layer in the active region; a gate electrode formed on the gate layer; a first insulating film that covers the gate electrode and that is formed on the AlGaN layer in the active region; and a second insulating film that covers the first insulating film and that is formed on the inactive region, wherein the second insulating film is a multi-layer film, the first insulating film is a nitride film, the second insulating film includes a lower layer and an upper layer, and the lower layer is thinner than the upper layer. 2 . The nitride semiconductor device according to claim 1 , further comprising an ohmic electrode that is formed on the first insulating film, that is covered with the second insulating film, and that is ohmically connected to the AlGaN layer through the first insulating film. 3 . The nitride semiconductor device according to claim 2 , wherein the ohmic electrode includes each of the source contacts and each of the drain contacts between which the gate electrode is placed. 4 . The nitride semiconductor device according to claim 1 , wherein the gate layer is formed in a self-aligned manner with respect to the gate electrode. 5 . The nitride semiconductor device according to claim 1 , wherein the concave portion has a depth deeper than a depth position of a two-dimensional electron gas in the layered structure of the active region. 6 . The nitride semiconductor device according to claim 1 , wherein the concave portion has a side portion that is tilted with respect to a surface of the AlGaN layer. 7 . The nitride semiconductor device according to claim 1 , wherein the first insulating film has an end surface that in continuous with an end surface of the AlGaN layer. 8 . The nitride semiconductor device according to claim 1 , wherein a plurality of the gate electrodes are surrounded by the inactive region. 9 . The nitride semiconductor device according to claim 3 , wherein the source contact and the drain contact have a rectangle shape in a plan view, and the plurality of the source contacts and the drain contacts are alternately arranged such that long side directions thereof are parallel to each other. 10 . The nitride semiconductor device according to claim 1 , wherein the AlGaN layer has a thickness from 10 nm to 20 nm. 11 . The nitride semiconductor device according to claim 1 , wherein the first insulating film has a thickness from 90 nm to 110 nm. 12 . The nitride semiconductor device according to claim 1 , wherein the lower layer of the second insulating film has a thickness from 75 nm to 85 nm, and the upper layer of the second insulating film has a thickness from 0.8 μm to 1.2 μm. 13 . The nitride semiconductor device according to claim 1 , wherein the gate layer is made of a GaN layer doped with an acceptor-type impurity. 14 . The nitride semiconductor device according to claim 1 , wherein the bottom portion of the concave portion reaches an end surface of the GaN layer and intersects the end surface of the GaN layer.

Assignees

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Classifications

  • for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673) · CPC title

  • Nitride Group III-V materials, e.g. AlN or GaN · CPC title

  • H10D30/475Primary

    having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs · CPC title

  • of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT · CPC title

  • for FETs · CPC title

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What does patent US2025063787A1 cover?
A nitride semiconductor device includes a channel layer, a barrier layer made of Al x In y Ga 1-x-y N (x>0, x+y≤1), an active region that has a layered structure including the channel layer and the barrier layer, an inactive region that is formed at the layered structure around the active region and that is a concave portion having a bottom portion that reaches the channel layer, a gate layer m…
Who is the assignee on this patent?
Rohm Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D62/8503. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Feb 20 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).