P-type laterally diffused metal oxide semiconductor device and manufacturing method therefor

Patent metadata

Field	Value
Publication number	US-2025056834-A1
Application number	US-202218722930-A
Country	US
Kind code	A1
Filing date	Nov 30, 2022
Priority date	Feb 25, 2022
Publication date	Feb 13, 2025
Grant date	—

Abstract

A manufacturing method for a P-type laterally diffused metal oxide semiconductor device includes: forming a N-type buried layer in a substrate, forming a P-type region located on the N-type buried layer, and forming a mask layer located on the P-type region; patterning the mask layer to form at least two injection windows; performing N-type ion implantation by the at least two injection windows; forming an oxide layer; removing the mask layer; performing P-type ion implantation on the P-type region to form a P-type doped region; diffusing the P-type doped region to form a drift region and two P-type well regions, diffusing the high-voltage N-well doped region to form a high-voltage N-type well region, and diffusing the low-voltage N-well doped region to form a low-voltage N-type well region; and forming a source doped region, a drain doped region, and a gate.

First claim

1 . A method for manufacturing a P-type laterally diffused metal oxide semiconductor device, comprising:
forming an N-type buried layer in a substrate, forming a P-type region on the N-type buried layer, and forming a mask layer on the P-type region; patterning the mask layer to form at least two implantation windows; performing an N-type ion implantation through the at least two implantation windows to form a high-voltage N-well doped region and a low-voltage N-well doped region in the P-type region, wherein a doping concentration of the low-voltage N-well doped region is higher than a doping concentration of the high-voltage N-well doped region; forming an oxide layer on a surface of the P-type region at each implantation window; removing at least a part of the mask layer; performing a P-type ion implantation on the P-type region to form a P-type doped region; diffusing the P-type doped region by a thermal annealing to form a drift region and two P-type well regions, diffusing the high-voltage N-well doped region to form a high-voltage N-type well region, and diffusing the low-voltage N-well doped region to form a low-voltage N-type well region; wherein the drift region is located between the high-voltage N-type well region and the low-voltage N-type well region, the two P-type well regions are located on two sides of the high-voltage N-type well region, respectively, and one of the two P-type well region is located between the high-voltage N-type well region and the drift region; and forming a source doped region, a drain doped region, and a gate; wherein the source doped region is located in the low-voltage N-type well region, the drain doped region is located in one P-type well region and is located between the high-voltage N-type well region and the drift region, the gate is located between the source doped region and the drain doped region, and the source doped region and the drain doped region have P-type doping.

2 . The method according to claim 1 , wherein the at least two implantation windows comprise a high-voltage N-well implantation window and a low-voltage N-well implantation window;
performing the N-type ion implantation through each implantation window and forming the high-voltage N-well doped region and the low-voltage N-well doped region in the P-type region comprises: performing a first N-type ion implantation through the high-voltage N-well implantation window and the low-voltage N-well implantation window to form the high-voltage N-well doped region; forming a photoresist layer on the P-type region, the photoresist layer covering the high-voltage N-well implantation window and exposing the low-voltage N-well implantation window; and performing a second N-type ion implantation through the low-voltage N-well implantation window to form the low-voltage N-well doped region in the P-type region.

3 . The method according to claim 2 , wherein the at least two implantation windows further comprise a plurality of N-type ion implantation windows located between the high-voltage N-well implantation window and the low-voltage N-well implantation window;
wherein performing the first N-type ion implantation comprises: forming a corresponding number of N-type drift region doping adjustment regions in the P-type region through the plurality of N-type ion implantation windows; and covering the plurality of N-type ion implantation windows by the photoresist layer.

4 . The method according to claim 3 , wherein adjacent windows in the plurality of N-type ion implantation windows are spaced apart by 1.0 to 2.0 microns.

5 . The method according to claim 3 , wherein a width of each N-type ion implantation window is 2.0 to 4.0 microns.

6 . The method according to claim 3 , wherein a dosage of the P-type ion implantation is greater than a dosage of the first N-type ion implantation.

7 . The method according to claim 1 , wherein the mask layer comprises a silicon dioxide layer and a silicon nitride layer located on the silicon dioxide layer, and the step of removing at least a part of the mask layer is to remove the silicon nitride layer.

8 . The method according to claim 1 , wherein prior to forming the gate, the method further comprises:
forming a field effect oxide layer on the drift region, wherein the field effect oxide layer is located between the source doped region and the drain doped region; wherein the gate is a polycrystalline silicon gate extending onto the field effect oxide layer.

9 . The method according to claim 8 , further comprising:
forming a source metal electrode, a drain metal electrode, and a gate metal electrode; wherein the source metal electrode is located on the source doped region and is electrically connected to the source doped region, the drain metal electrode is located on the drain doped region and is electrically connected to the drain doped region, the gate metal electrode is located on the gate and is electrically connected to the gate, a part of the drain metal electrode located above the field effect oxide layer serves as a drain metal field plate, and a part of the gate metal electrode located above the field effect oxide layer serves as a gate metal field plate.

10 . The method according to claim 1 , further comprising:
forming a substrate leading-out region, wherein the substrate leading-out region is formed in a P-type well region on a side of the high-voltage N-type well region away from the drift region, and the substrate leading-out region has P-type doping; and forming a body region in the low-voltage N-type well region, wherein the body region has N-type doping, and the source doped region is located between the body region and the drift region.

11 . The method according to claim 1 , wherein an N-type ion source for the N-type ion implantation is phosphorus, and a doping concentration thereof is 1e11 cm −2 to 1e13 cm −2 ; and a P-type ion source for the P-type ion implantation is boron, and a doping concentration thereof is 1e11 cm −2 to 1e13 cm −2 .

12 . The method according to claim 1 , wherein a doping concentration of the drift region is less than a doping concentration of the P-type well region.

13 . The method according to claim 1 , wherein both the high-voltage N-type well region and the low-voltage N-type well region are in contact with the N-type buried layer.

14 . A P-type laterally diffused metal oxide semiconductor device, comprising:
a substrate; an N-type buried layer provided in the substrate; a P-type region provided on the N-type buried layer and the substrate; a high-voltage N-type well region, a low-voltage N-type well region, a drift region, and two P-type well regions that are provided in the P-type region; a field effect oxide layer provided on the P-type region; a gate located on the low-voltage N-type well region and the field effect oxide layer; a body region and a source doped region that are provided in the low-voltage N-type well region, wherein the body region is connected to a body region metal electrode, and the source doped region is located between the gate and the body region and is connected to a source metal electrode; a substrate leading-out region provided in one of the two P-type well regions and connected to a substrate leading-out region metal electrode; and a drain doped region provided in another of the two P-type well regions, wherein the drain doped region is located between the high-voltage N-type well region and the drift region and is connected to a drain metal electrode.

15 . The P-type laterally diffused metal oxide semiconductor device according to claim 14 , wherein a doping c

Assignees

• Univ Southeast
• Csmc Technologies Fab2 Co Ltd

Inventors

• Zhang Long
• He Nailong
• Cui Yongjiu
• Zhang Sen
• Wang Xiaona
• Lin Feng
• Ma Jie
• Liu Siyang
• Sun Weifeng

Classifications

• H10P30/22 Primary

  using masks · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D62/106

  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions · CPC title

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title