Quadrature noise shapingsar adc and operation method thereof

Patent metadata

Field	Value
Publication number	US-2025055469-A1
Application number	US-202418750104-A
Country	US
Kind code	A1
Filing date	Jun 21, 2024
Priority date	Aug 11, 2023
Publication date	Feb 13, 2025
Grant date	—

Abstract

An analog-to-digital converter ADC includes a first successive approximation register analog-to-digital converter (SAR ADC) configured to convert an in-phase input signal to digital data using a first integrator, a second successive approximation register analog-to-digital converter (SAR ADC) configured to convert a quadrature input signal to digital data using a second integrator, and first to fourth sampling capacitors configured to transmit an output of the first integrator to an input terminal of the second integrator, and transmit an output of the second integrator to an input terminal of the first integrator when the first integrator and the second integrator integrate the sampled in-phase input signal and the quadrature input signal, respectively. The first and second SAR ADCs and the first to fourth sampling capacitors are driven according to an operation sequence of a sampling stage, a conversion stage, and an integration stage.

First claim

What is claimed is:

1 . An analog-to-digital converter (ADC), comprising:
a first successive approximation register analog-to-digital converter (SAR ADC) configured to convert an in-phase input signal to digital data using a first integrator; a second successive approximation register analog-to-digital converter (SAR ADC) configured to convert a quadrature input signal to digital data using a second integrator; and first to fourth sampling capacitors configured to transmit an output of the first integrator to an input terminal of the second integrator, and transmit an output of the second integrator to an input terminal of the first integrator when the first integrator and the second integrator integrate the converted in-phase input signal and the converted quadrature input signal, respectively, wherein the first and second SAR ADCs and the first to fourth sampling capacitors are driven according to an operation sequence of a sampling stage, a conversion stage, and an integration stage.

2 . The ADC of claim 1 , wherein the first SAR ADC includes a first Capacitive Analog-to-Digital Converter (CADC) that samples the in-phase input signal, and the second SAR ADC includes a second CADC that samples the quadrature input signal,
wherein the first CADC includes a first main capacitor and a first cross-couple capacitor, and the second CADC includes a second main capacitor and a second cross-couple capacitor.

3 . The ADC of claim 2 , wherein in the conversion stage, the first main capacitor and the first cross-couple capacitor are connected to a first comparator, and the second main capacitor and the second cross-couple capacitor are connected to a second comparator.

4 . The ADC of claim 3 , wherein in the integration stage, the first main capacitor is connected to the first integrator, the first cross-couple capacitor is connected to the second integrator, the second main capacitor is connected to the second integrator, and the second cross-couple capacitor is connected to the second integrator.

5 . The ADC of claim 4 , wherein in the integration stage:
the first sampling capacitor is configured to sample an integration result of the first integrator, and the fourth sampling capacitor is configured to sample an integration result of the second integrator, the second sampling capacitor is configured to transmit the integration result of the first integrator sampled in a previous integration stage to the second integrator, and the third sampling capacitor is configured to transmit the integration result of the second integrator sampled in the previous integration stage to the first integrator.

6 . The ADC of claim 5 , wherein in the previous integration stage:
the second sampling capacitor is configured to sample an integration result of the first integrator, and the third sampling capacitor is configured to sample an integration result of the second integrator, the first sampling capacitor is configured to transmit the sampled integration result of the first integrator to the second integrator, and the fourth sampling capacitor is configured to transmit the sampled integration result of the second integrator to the first integrator.

7 . The ADC of claim 6 , further comprising:
a switch unit configured to connect the first to fourth sampling capacitors to the input terminal or the output terminal of the first integrator and the second integrator in the integration stage and the previous integration stage.

8 . The ADC of claim 6 , wherein the sampling stage and the conversion stage are performed between the previous integration stage and the integration stage.

9 . The ADC of claim 2 , further comprising:
a first cross-couple switch configured to connect the first cross-couple capacitor to the input terminal of the second integrator in the integration stage; and a second cross-couple switch configured to connect the second cross-couple capacitor to the input terminal of the first integrator in the integration stage.

10 . An operation method of a noise shaping successive approximation register analog-to-digital converter (NS-SAR ADC), comprising:
sampling an in-phase input signal by a first Capacitive Analog-to-Digital Converter (CADC) of a first successive approximation register analog-to-digital converter (SAR ADC) and a quadrature input signal by a second CADC of a second SAR ADC; converting the in-phase input signal sampled by the first CADC and the quadrature input signal sampled by the second CADC into digital signals using a first comparator and a second comparator, respectively; and integrating, a combined signal of an in-phase residue remaining in the first CADC and a first cross-couple residue transmitted from the second CADC by a first integrator, and a combined signal of a quadrature residue remaining in the second CADC and a second cross-couple residue transmitted from the first CADC, respectively.

11 . The method of claim 10 , wherein when integrating, an integration result of the first integrator sampled in a previous integration operation is transmitted to the second integrator, and an integration result of the second integrator sampled in the previous integration operation is transmitted to the first integrator.

12 . The method of claim 11 , wherein when integrating, the integration result of the first integrator and the integration result of the second integrator are sampled in corresponding sampling capacitors.

13 . The method of claim 11 , wherein when integrating, the integration result of the first integrator is sampled, and the integration result of the first integrator sampled in the previous integration step is cross-transferred to the input terminal of the second integrator.

14 . The method of claim 13 , wherein when integrating, the integration result of the second integrator is sampled, and the integration result of the second integrator sampled in the previous integration step is cross-transferred to the input terminal of the first integrator.

15 . The method of claim 10 , wherein the second cross-couple residue is inverted and transmitted to the second integrator.

16 . An analog-to-digital converter, comprising:
a first noise shaping successive approximation register analog-to-digital converter (NS-SAR ADC) configured to convert an in-phase input signal into digital data; and a second noise shaping successive approximation register analog-to-digital converter (NS-SAR ADC) configured to convert a quadrature input signal into digital data, wherein the first NS-SAR ADC integrates a first residue obtained by subtracting an in-phase output from the in-phase input signal, and the second NS-SAR ADC integrates a second residue obtained by subtracting a quadrature output from the quadrature input signal, wherein a portion of the first residue is transmitted to the second NS-SAR ADC, and a portion of the second residue is transmitted to the first NS-SAR ADC.

17 . The ADC of claim 16 , wherein the first NS-SAR ADC includes a first cross-couple capacitor that samples and transmits the portion of the first residue, and the second NS-SAR ADC includes a second cross-couple capacitor that samples and transmits the portion of the second residue.

18 . The ADC of claim 17 , wherein the portion of the second residue is inverted and transmitted to the integrator of the first NS-SAR ADC.

19 . The ADC of claim 17 , further comprising:
a first cross-couple switch configured to connect the first cross-couple capacitor to an input terminal of the in-phase input signal during a samplin

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jongmi
• Lee Jaehoon
• Cho Seongeun

Classifications

• H03M1/462 Primary

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/303

  Circuits or methods for processing the quadrature signals · CPC title

• H03M1/1245 Primary

  Details of sampling arrangements or methods · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03M1/16

  with scale factor modification, i.e. by changing the amplification between the steps {(H03M1/141 takes precedence)} · CPC title