Driver circuit for bypass power transistor including secondary supply input connection from a power delivery circuit

Patent metadata

Field	Value
Publication number	US-2025055453-A1
Application number	US-202318448255-A
Country	US
Kind code	A1
Filing date	Aug 11, 2023
Priority date	Aug 11, 2023
Publication date	Feb 13, 2025
Grant date	—

Abstract

A driver circuit is configured control one or more bypass transistors. The driver circuit includes a primary supply input connection configured to supply the driver circuit with power from a set of battery cells. The set of battery cells is configured to supply power to a load via a power delivery circuit. The driver circuit also includes one or more secondary supply input connections. The driver circuit is configured to receive information indicating whether an error condition is present in the power delivery circuit and control, based on the error condition being present in the power delivery circuit, the one or more bypass transistors to define a bypass current path. The driver circuit is also configured to receive, via a secondary supply input connection of the one or more secondary supply input connections, power from the bypass current path.

First claim

What is claimed is:

1 . A driver circuit configured control one or more bypass power transistors, the driver circuit comprising:
a primary supply input connection configured to supply the driver circuit with power from a set of battery cells, wherein the set of battery cells is configured to supply power to a load via a power delivery circuit; and one or more secondary supply input connections, wherein the driver circuit is configured to:
receive information indicating whether an error condition is present in the power delivery circuit;
control, based on the error condition being present in the power delivery circuit, the one or more bypass power transistors to define a bypass current path between the one or more bypass power transistors and the load; and
receive, via a secondary supply input connection of the one or more secondary supply input connections, power from the bypass current path, wherein the power from the bypass current path exceeds a power threshold for controlling the one or more bypass power transistors to define the bypass current path.

2 . The driver circuit of claim 1 ,
wherein the driver circuit is further configured to receive, via the primary supply input connection, the power from the set of battery cells when the error condition is present in the power delivery circuit, and wherein the power from the set of battery cells does not exceed the power threshold for controlling the one or more bypass power transistors to define the bypass current path.

3 . The driver circuit of claim 1 , wherein the power threshold is a first power threshold, and wherein the driver circuit is further configured to:
control, based on the error condition not being present in the power delivery circuit, the one or more bypass power transistors to not define the bypass current path; and receive, via the primary supply input connection, power from the set of battery cells that exceeds a second power threshold for controlling the one or more bypass power transistors not to define the bypass current path.

4 . The driver circuit of claim 1 , wherein the one or more secondary supply input connections comprises:
a first secondary supply input connection configured to supply the driver circuit with power from a first node of the bypass current path when the error condition is present at a first node of the power delivery circuit; and a second secondary supply input connection configured to supply the driver circuit with power from a second node of the bypass current path when the error condition is present at a second node of the power delivery circuit.

5 . The driver circuit of claim 4 , wherein the power delivery circuit comprises two or more power transistors, wherein the first node of the power delivery circuit comprises a first power transistor of the two or more power transistors, and wherein the second node of the power delivery circuit comprises a second power transistor of the two or more power transistors.

6 . The driver circuit of claim 1 , wherein the power delivery circuit comprises an H-bridge circuit including a first power transistor, a second power transistor, a third power transistor, and a fourth power transistor, and
wherein the error condition comprises a failure of one or more of the first power transistor, the second power transistor, the third power transistor, and the fourth power transistor.

7 . The driver circuit of claim 6 , wherein the H-bridge circuit is configured to:
supply, according to a first operating mode, zero voltage to the load when the first power transistor and the second power transistor are turned on and the third power transistor and the fourth power transistor are turned off; supply, according to a second operating mode, a positive voltage to the load when the first power transistor and the fourth power transistor are turned on and the second power transistor and the third power transistor are turned off; supply, according to a third operating mode, zero voltage to the load when the first power transistor and the second power transistor are turned off and the third power transistor and the fourth power transistor are turned on; and supply, according to a fourth operating mode, a negative voltage to the load when the first power transistor and the fourth power transistor are turned off and the second power transistor and the third power transistor are turned on, wherein the error condition comprising the failure of one or more of the first power transistor, the second power transistor, the third power transistor, and the fourth power transistor prevents the H-bridge circuit from operating according to one or more of the first operating mode, the second operating mode, the third operating mode, and the fourth operating mode.

8 . The driver circuit of claim 1 , wherein the one or more bypass power transistors comprise a first bypass power transistor and a second bypass power transistor placed in an anti-series arrangement so that a body diode of the first bypass power transistor faces a first direction and a body diode of the second bypass power transistor faces a second direction opposite the first direction.

9 . The driver circuit of claim 1 , wherein to control the one or more bypass power transistors to define the bypass current path, the driver circuit is configured to:
apply a voltage to a gate terminal of each bypass power transistor of the one or more bypass power transistors that is sufficient to turn on the one or more bypass power transistors so that current flows across the one or more bypass power transistors, wherein the voltage sufficient to turn on the one or more bypass power transistors corresponds to the power threshold for controlling the one or more bypass power transistors to define the bypass current path.

10 . The driver circuit of claim 1 ,
wherein the error condition present in the power delivery circuit causes a current avalanche, and wherein the current avalanche causes the driver circuit to receive power from the bypass current path that exceeds the power threshold for controlling the one or more bypass power transistors to define the bypass current path.

11 . The driver circuit of claim 1 , wherein the load comprises an electrical motor of a vehicle.

12 . The driver circuit of claim 11 , wherein the power delivery circuit comprises an H-bridge circuit configured as a step-wise inverter circuit for controlling the electrical motor of the vehicle.

13 . A method for controlling one or more bypass power transistors, the method comprising:
supplying, by a primary supply input connection of a driver circuit, the driver circuit with power from a set of battery cells, wherein the set of battery cells is configured to supply power to a load via a power delivery circuit; receiving, by the driver circuit, information indicating whether an error condition is present in the power delivery circuit; controlling, by the driver circuit based on the error condition being present in the power delivery circuit, the one or more bypass power transistors to define a bypass current path for bypassing the power delivery circuit; and receiving, by the driver circuit via a secondary supply input connection of the one or more secondary supply input connections, power from the bypass current path, wherein the power from the bypass current path exceeds a power threshold for controlling the one or more bypass power transistors to define the bypass current path.

14 . The method of claim 13 , further comprising:
receiving, by the driver circuit via the primary supply input connection, the power from the set of battery cells when the error condition

Assignees

• Infineon Technologies Ag

Inventors

• Mourrier Andre

Classifications

• H02J7/855

  with circuits adapted for supplying loads from the battery · CPC title

• H01M2010/4271

  Battery management systems including electronic circuits, e.g. control of current or voltage to keep battery in healthy state, cell balancing · CPC title

• H02J2207/20

  Charging or discharging characterised by the power electronics converter · CPC title

• H01M10/4207

  for several batteries or cells simultaneously or sequentially · CPC title

• H01M10/4257

  Smart batteries, e.g. electronic circuits inside the housing of the cells or batteries · CPC title