Configurable capacitor

Patent metadata

Field	Value
Publication number	US-2025048661-A1
Application number	US-202418924884-A
Country	US
Kind code	A1
Filing date	Oct 23, 2024
Priority date	Oct 20, 2021
Publication date	Feb 6, 2025
Grant date	—

Abstract

A capacitance device includes: a semiconductor substrate; a capacitor disposed on the semiconductor substrate and including first and second positive terminals and first and second negative terminals; a passivation layer formed over the capacitor, the first and second positive terminals and the first and second negative terminals, the passivation layer defining first and second openings over the first and second positive terminals, respectively, a third opening over the first negative terminal and a fourth opening over the second negative terminal; a first metallic bump disposed on the passivation layer and including first extending portions that extend through each of the first and second openings, electrically coupling the first and second positive terminals; and a second metallic bump disposed on the passivation layer and including second extending portions that extend through each of the third and fourth openings, electrically coupling the first and second negative terminals.

First claim

What is claimed is:

1 . A capacitance device, comprising:
a semiconductor substrate; a capacitor disposed on the semiconductor substrate, the capacitor including first and second positive terminals and first and second negative terminals; a passivation layer formed over the capacitor, the first and second positive terminals and the first and second negative terminals, the passivation layer defining a first opening over the first positive terminal, a second opening over the second positive terminal, a third opening over the first negative terminal and a fourth opening over the second negative terminal; a first metallic bump disposed adjacent to the passivation layer and including first extending portions that extend through each of the first and second openings, electrically coupling the first positive terminal to the second positive terminal; and a second metallic bump disposed adjacent to the passivation layer and including second extending portions that extend through each of the third and fourth openings, electrically coupling the first negative terminal to the second negative terminal.

2 . The capacitance device of claim 1 , wherein the first positive terminal is electrically coupled to the second positive terminal via a first external connection, and wherein the first negative terminal is electrically coupled to the second negative terminal via a second external connection.

3 . The capacitance device of claim 2 , wherein the first external connection is a first metallic connector disposed on the passivation layer and extending from the first positive terminal to the second positive terminal, and wherein the second external connection is a second metallic connector disposed on the passivation layer and extending from the first negative terminal to the second negative terminal.

4 . The capacitance device of claim 2 , wherein the first and second external connections are disposed on a separate interconnect board that is electrically coupled to the capacitance device.

5 . The capacitance device of claim 1 , wherein the capacitor is a first capacitor, the capacitance device further comprising a second capacitor disposed on the semiconductor substrate and including a third positive terminal that is coupled to the first positive terminal of the first capacitor, the second capacitor including and a third negative terminal that is coupled to the first negative terminal of the first capacitor.

6 . The capacitance device of claim 5 , wherein the third positive terminal is coupled to the first positive terminal via a first electrical conductor disposed on the semiconductor substrate, and wherein the third negative terminal is coupled to the first negative terminal via a second electrical conductor disposed on the semiconductor substrate.

7 . The capacitance device of claim 5 , wherein the third positive terminal is coupled to the first positive terminal via a first external connection disposed on a separate electronic device that is coupled to the capacitance device, and wherein the third negative terminal is coupled to the first negative terminal via a second external connection that is disposed on the separate electronic device.

8 . The capacitance device of claim 1 , wherein each the first and the second metallic bumps are coupled to an external load, and wherein the capacitor is a first capacitor, the capacitance device further comprising a second capacitor disposed on the semiconductor substrate and including a third positive terminal and a third negative terminal that are each coupled to the external load.

9 . The capacitance device of claim 8 , wherein the first metallic bump is electrically connected to the third positive terminal and wherein the second metallic bump is electrically connected to the third negative terminal.

10 . The capacitance device of claim 8 , wherein the first capacitor is electrically isolated from the second capacitor.

11 . A capacitance device, comprising:
a semiconductor substrate; a capacitor disposed on the semiconductor substrate, the capacitor including first and second positive terminals and first and second negative terminals; a passivation layer formed over the capacitor, the first and second positive terminals and the first and second negative terminals, the passivation layer defining a first opening over the first positive terminal, a second opening over the second positive terminal, a third opening over the first negative terminal and a fourth opening over the second negative terminal; a first electrical connection disposed adjacent to the passivation layer and including a first extending portion that extends through the first opening, the first electrical connection further including a second extending portion that extends through the second opening, wherein the first positive terminal is electrically terminable to the second positive terminal via a first external electrical connector; and a second electrical connection disposed adjacent to the passivation layer and including a third extending portion that extends through the third opening, the second electrical connection further including a fourth electrical connection that extends through the fourth opening, wherein the first negative terminal is electrically terminable to the second negative terminal via a second external electrical connector.

12 . The capacitance device of claim 11 , wherein the first external connector is a first metallic structure disposed on the passivation layer and extending from the first positive terminal to the second positive terminal, and wherein the second external connector is a second metallic structure disposed on the passivation layer and extending from the first negative terminal to the second negative terminal.

13 . The capacitance device of claim 11 , wherein the first and second external connectors are disposed on a separate interconnect board that is electrically coupled to the capacitance device.

14 . The capacitance device of claim 11 , wherein the capacitor is a first capacitor, the capacitance device further comprising a second capacitor disposed on the semiconductor substrate and including a third positive terminal that is coupled to the first positive terminal of the first capacitor, the second capacitor including and a third negative terminal that is coupled to the first negative terminal of the first capacitor.

15 . The capacitance device of claim 14 , wherein the third positive terminal is coupled to the first positive terminal via a first electrical conductor disposed on the semiconductor substrate, and wherein the third negative terminal is coupled to the first negative terminal via a second electrical conductor disposed on the semiconductor substrate.

16 . The capacitance device of claim 14 , wherein the third positive terminal is coupled to the first positive terminal via a first electrically conductive structure disposed on a separate electronic device that is coupled to the capacitance device, and wherein the third negative terminal is coupled to the first negative terminal via a second electrically conductive structure disposed on the separate electronic device.

17 . The capacitance device of claim 11 , wherein each the first and the second electrical connections are coupled to a separate external load, and wherein the capacitor is a first capacitor, the capacitance device further comprising a second capacitor disposed on the semiconductor substrate and including a third positive terminal and a third negative terminal that are each coupled to the separate external load.

18 . The capaci

Assignees

• Empower Semiconductor Inc

Inventors

• Der Minassians Artin
• Phillips Timothy Alan
• Roessig Trey
• Huang Peter
• Oak Parag

Classifications

• H10D1/692

  Electrodes · CPC title

• H10D1/714 Primary

  having horizontal extensions · CPC title

• H01L28/86 Primary

  Electricity · mapped topic