Multiplexer with highly linear analog switch

Patent metadata

Field	Value
Publication number	US-2025047279-A1
Application number	US-202418920681-A
Country	US
Kind code	A1
Filing date	Oct 18, 2024
Priority date	Dec 2, 2020
Publication date	Feb 6, 2025
Grant date	—

Abstract

A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.

First claim

1 . A method, comprising:
passing a signal from an input terminal of a multiplexer through a main transistor of the multiplexer to an output terminal of the multiplexer; coupling a first bootstrap capacitor between a gate terminal and a source terminal of the main transistor during a first phase; and coupling a second bootstrap capacitor between the gate terminal and the source terminal of the main transistor during a second phase alternating with the first phase.

2 . The method of claim 1 , further comprising:
decoupling the first bootstrap capacitor from the gate and source terminals during the second phase; and decoupling the second bootstrap capacitor from the gate and source terminals during the first phase.

3 . The method of claim 2 , further comprising:
charging the first bootstrap capacitor to a supply voltage value during the second phase; and charging the second bootstrap capacitor to the supply voltage value during the first phase.

4 . The method of claim 3 , further comprising maintaining a gate to source voltage of the main transistor at the supply voltage value during the first phase and the second phase.

5 . The method of claim 4 , further comprising alternating between the first phase and the second phase based on a clock signal.

6 . The method of claim 5 , wherein coupling and decoupling the first bootstrap capacitor includes controlling a plurality of first switches based on the clock signal.

7 . The method of claim 6 , wherein coupling and decoupling the second bootstrap capacitor includes controlling a plurality of second switches based on the clock signal.

8 . An integrated circuit, comprising:
a multiplexer, including:
an input;
an output;
a main transistor having a source terminal coupled to the input, a drain terminal coupled to the output, and a gate terminal;
a first bootstrap circuit coupled to the input, the first bootstrap circuit including:
a first pair of transistors;
a first bootstrap capacitor; and
a second pair of transistors, the first bootstrap capacitor coupled between the first pair of transistors and the second pair of transistors; and

a second bootstrap circuit coupled to the input, the second bootstrap circuit including:
a third pair of transistors;
a second bootstrap capacitor; and
a fourth pair of transistors, the second bootstrap capacitor coupled between the third pair of transistors and the fourth pair of transistors.

9 . The integrated circuit of claim 8 , further comprising an analog-to-digital converter configured to receive a signal from the output and to convert the signal to a digital signal.

10 . The integrated circuit of claim 8 , wherein the first bootstrap circuit is configured to receive a first clock signal, a second clock signal, and a first phase signal 180 degrees out of phase with the first clock signal, and wherein the second bootstrap circuit is configured to receive the first clock signal, the second clock signal, and a second phase signal 180 degrees out of phase with the second clock signal.

11 . An integrated circuit, comprising:
a multiplexer, including:
an input;
an output;
a main transistor having a source terminal coupled to the input, a drain terminal coupled to the output, and a gate terminal;
a first bootstrap circuit coupled to the input; and
a second bootstrap circuit coupled to the input.

12 . The integrated circuit of claim 11 , wherein the first bootstrap circuit includes:
a first pair of transistors; a first bootstrap capacitor; and a second pair of transistors.

13 . The integrated circuit of claim 12 , wherein the first bootstrap capacitor is coupled between the first pair of transistors and the second pair of transistors.

14 . The integrated circuit of claim 12 , wherein the second bootstrap circuit includes:
a third pair of transistors; a second bootstrap capacitor; and a fourth pair of transistors.

15 . The integrated circuit of claim 14 , wherein the second bootstrap capacitor is coupled between the third pair of transistors and the fourth pair of transistors.

16 . The integrated circuit of claim 14 , wherein the first bootstrap capacitor is coupled between the first pair of transistors and the second pair of transistors, and the second bootstrap capacitor is coupled between the third pair of transistors and the fourth pair of transistors.

17 . The integrated circuit of claim 11 , wherein the main transistor includes a field effect transistor.

18 . The integrated circuit of claim 11 , wherein the main transistor is configured to have a substantially constant resistance during operation.

19 . The integrated circuit of claim 11 , wherein the first bootstrap circuit includes a phase generation circuit configured to:
produce a phase signal to selectively decouple a bootstrap capacitor of the first bootstrap circuit from the input.

20 . The integrated circuit of claim 11 , further comprising a phase generation circuit configured to produce a phase signal to selectively decouple the input from at least one bootstrap capacitor of the first bootstrap circuit or the second bootstrap circuit.

Assignees

• St Microelectronics Int Nv

Inventors

• Garg Vaibhav
• Jain Abhishek
• Kumar Anand

Classifications

• H03K19/01735

  by bootstrapping, i.e. by positive feed-back · CPC title

• H03K17/693 Primary

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title

• H03K17/6874

  in a symmetrical configuration · CPC title

• H03K2217/0054

  Gating switches, e.g. pass gates · CPC title

• H03K17/6872 Primary

  using complementary field-effect transistors · CPC title