Memory configured to perform a channel precharge operation and method of operating the memory

Patent metadata

Field	Value
Publication number	US-2025046385-A1
Application number	US-202318515975-A
Country	US
Kind code	A1
Filing date	Nov 21, 2023
Priority date	Aug 3, 2023
Publication date	Feb 6, 2025
Grant date	—

Abstract

A memory includes a cell string including a first select transistor, cell transistors, and a second select transistor and a row circuit configured to drive a first select line for controlling the first select transistor, a second select line for controlling the second select transistor and word lines for controlling the cell transistors. The row circuit differently performs a discharge operation of the first select line according to a position in the cell string of a program target cell transistor.

First claim

What is claimed is:

1 . A memory comprising:
a cell string including a first select transistor, a plurality of cell transistors, and a second select transistor; and a row circuit configured to drive a first select line for controlling the first select transistor, a second select line for controlling the second select transistor and word lines for controlling the cell transistors, wherein the row circuit differently performs a discharge operation of the first select line according to a position in the cell string of a program target cell transistor from the plurality of cell transistors.

2 . The memory of claim 1 ,
wherein the plurality of cell transistors are sequentially programmed in an order starting from a cell transistor of the plurality of cell transistors closer to the second select transistor to a cell transistor of the plurality of cell transistors farther from the second select transistor, wherein the plurality of cell transistors are divided into two or more groups according to a distance from the second select transistor, and wherein the row circuit differently performs the discharge operation of the first select line according to which group of the two or more groups the program target cell transistor belongs to.

3 . The memory of claim 2 , wherein the row circuit adjusts a length of a discharge period of the first select line to be shorter as the program target cell transistor belongs to a group closer to the second select transistor among the groups.

4 . The memory of claim 2 , wherein the row circuit adjusts an absolute value of a discharge slope of the first select line as the program target cell transistor belongs to a group closer to the second select transistor among the groups.

5 . The memory of claim 1 , wherein the discharge operation is performed after a channel precharge operation.

6 . The memory of claim 1 , wherein the discharge operation is performed after a verify operation.

7 . The memory of claim 1 , wherein the row circuit differently performs a discharge operation of the word lines according to the position in the cell string of the program target cell transistor.

8 . The memory of claim 1 ,
wherein the first select transistor is a source select transistor, and wherein the second select transistor is a drain select transistor.

9 . A method of operating a memory including a cell string including a first select transistor, a second select transistor, cell transistors of a first group, and cell transistors of a second group located farther from the second select transistor than the first group, the method comprising:
determining to perform a program operation of a first select cell transistor belonging to the first group; performing a channel precharge step of applying activation voltages to:
a first select line controlling the first select transistor;
a second select line controlling the second select transistor; and
word lines controlling the cell transistors of the first group and the second group;
performing a first discharge step of discharging the first select line, the second select line, and the word lines; programming the first select cell transistor; determining to perform a program operation of a second select cell transistor belonging to the second group; performing a channel precharge step of applying activation voltages to the first select line controlling the first select transistor, the second select line controlling the second select transistor, and the word lines controlling the cell transistors of the first group and the second group; performing a second discharge step of discharging the first select line, the second select line, and the word lines, and discharging the first select line more slowly than in the first discharge step; and programming the second select cell transistor.

10 . The method of claim 9 , wherein performance of the discharge of the word lines in the second discharge step is performed more slowly than the discharge of the word lines in the first discharge step.

Assignees

• Sk Hynix Inc

Inventors

• Lee Hee Youl

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/3427 Primary

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title